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https://github.com/YosysHQ/yosys
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a7c8651b76
Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878. Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands. Helpful for when you want to run the same set of commands on a bunch of sv files.
47 lines
1 KiB
Text
47 lines
1 KiB
Text
read_rtlil << EOF
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module \top
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wire input 1 \clk
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wire output 1 \o
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memory size 2 offset 1 \my_array
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cell $meminit \bad_init
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parameter \WORDS 1
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parameter \MEMID "\\my_array"
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parameter \ABITS 32
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parameter \WIDTH 1
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parameter \PRIORITY 1
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connect \ADDR 0
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connect \DATA 1'0
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end
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cell $memwr \bad_wr
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parameter \MEMID "\\my_array"
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parameter \CLK_ENABLE 1
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parameter \CLK_POLARITY 1
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parameter \PRIORITY 1
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parameter \ABITS 2
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parameter \WIDTH 1
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connect \EN 1'1
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connect \CLK \clk
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connect \ADDR 2'00
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connect \DATA 1'0
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end
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cell $memrd \bad_rd
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parameter \MEMID "\\my_array"
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parameter \CLK_ENABLE 0
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parameter \CLK_POLARITY 1
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parameter \TRANSPARENT 0
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parameter \ABITS 2
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parameter \WIDTH 1
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connect \CLK 1'x
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connect \EN 1'x
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connect \ADDR 2'11
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connect \DATA \o
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end
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end
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EOF
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logger -expect warning "initializes address 0" 1
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logger -expect warning "writes address 0" 1
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logger -expect warning "reads address 3" 1
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check_mem
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logger -check-expected
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design -reset
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