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Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()

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This commit is contained in:
Robert O'Callahan 2025-09-16 23:02:16 +00:00
parent d1fd6de6da
commit a7c46f7b4a
25 changed files with 54 additions and 54 deletions
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6
passes/cmds/check.cc
View file

@ -323,7 +323,7 @@ struct CheckPass : public Pass {
string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state));
for (auto str : wire_drivers[state])
message += stringf(" %s\n", str);
log_warning("%s", message.c_str());
log_warning("%s", message);
counter++;
}
@ -332,7 +332,7 @@ struct CheckPass : public Pass {
string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
for (auto str : it.second)
message += stringf(" %s\n", str);
log_warning("%s", message.c_str());
log_warning("%s", message);
counter++;
}
@ -418,7 +418,7 @@ struct CheckPass : public Pass {
prev = bit;
}
log_warning("%s", message.c_str());
log_warning("%s", message);
counter++;
}

8
passes/cmds/select.cc
View file

@ -658,7 +658,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
}
if (rem_objects == 0)
log_warning("reached configured limit at `%s'.\n", arg.c_str());
log_warning("reached configured limit at `%s'.\n", arg);
}
static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
@ -1002,14 +1002,14 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
if (it.second == false && !disable_empty_warning) {
std::string selection_str = select_blackboxes ? "=" : "";
selection_str += it.first;
log_warning("Selection \"%s\" did not match any module.\n", selection_str.c_str());
log_warning("Selection \"%s\" did not match any module.\n", selection_str);
}
}
for (auto &it : arg_memb_found) {
if (it.second == false && !disable_empty_warning) {
std::string selection_str = select_blackboxes ? "=" : "";
selection_str += it.first;
log_warning("Selection \"%s\" did not match any object.\n", selection_str.c_str());
log_warning("Selection \"%s\" did not match any object.\n", selection_str);
}
}
}
@ -1451,7 +1451,7 @@ struct SelectPass : public Pass {
while (std::getline(f, line)) {
size_t slash_pos = line.find('/');
if (slash_pos == string::npos) {
log_warning("Ignoring line without slash in 'select -read': %s\n", line.c_str());
log_warning("Ignoring line without slash in 'select -read': %s\n", line);
continue;
}
IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos));

4
passes/cmds/stat.cc
View file

@ -228,7 +228,7 @@ struct statdata_t {
cell_area.at(cell_type).is_sequential = cell_data.is_sequential;
} else {
log_warning("too small single_parameter_area %s width: %d size: %d\n", cell_type.c_str(), max_width,
log_warning("too small single_parameter_area %s width: %d size: %d\n", cell_type, max_width,
(int)cell_data.single_parameter_area.size());
cell_area.at(cell_type).area = cell_data.single_parameter_area.back();
cell_area.at(cell_type).is_sequential = cell_data.is_sequential;
@ -274,7 +274,7 @@ struct statdata_t {
cell_data.double_parameter_area.at(width_a - 1).at(width_b - 1);
cell_area.at(cell_type).is_sequential = cell_data.is_sequential;
} else {
log_warning("too small double_parameter_area %s, width_a: %d, width_b: %d, size_a: %d, size_b: %d\n", cell_type.c_str(),
log_warning("too small double_parameter_area %s, width_a: %d, width_b: %d, size_a: %d, size_b: %d\n", cell_type,
width_a, width_b, (int)cell_data.double_parameter_area.size(),
(int)cell_data.double_parameter_area.at(width_a - 1).size());
cell_area.at(cell_type).area = cell_data.double_parameter_area.back().back();

2
passes/cmds/timeest.cc
View file

@ -403,7 +403,7 @@ struct TimeestPass : Pass {
for (auto m : d->selected_modules()) {
if (!m->wire(RTLIL::escape_id(clk))) {
log_warning("No domain '%s' in module %s\n", clk.c_str(), log_id(m));
log_warning("No domain '%s' in module %s\n", clk, log_id(m));
continue;
}

8
passes/equiv/equiv_add.cc
View file

@ -61,7 +61,7 @@ struct EquivAddPass : public Pass {
if (gold_cell == nullptr) {
if (try_mode) {
log_warning("Can't find gold cell '%s'.\n", args[2].c_str());
log_warning("Can't find gold cell '%s'.\n", args[2]);
return;
}
log_cmd_error("Can't find gold cell '%s'.\n", args[2]);
@ -69,7 +69,7 @@ struct EquivAddPass : public Pass {
if (gate_cell == nullptr) {
if (try_mode) {
log_warning("Can't find gate cell '%s'.\n", args[3].c_str());
log_warning("Can't find gate cell '%s'.\n", args[3]);
return;
}
log_cmd_error("Can't find gate cell '%s'.\n", args[3]);
@ -126,7 +126,7 @@ struct EquivAddPass : public Pass {
if (!SigSpec::parse(gate_signal, module, args[2])) {
if (try_mode) {
log_warning("Error in gate signal: %s\n", args[2].c_str());
log_warning("Error in gate signal: %s\n", args[2]);
return;
}
log_cmd_error("Error in gate signal: %s\n", args[2]);
@ -134,7 +134,7 @@ struct EquivAddPass : public Pass {
if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1])) {
if (try_mode) {
log_warning("Error in gold signal: %s\n", args[1].c_str());
log_warning("Error in gold signal: %s\n", args[1]);
return;
}
log_cmd_error("Error in gold signal: %s\n", args[1]);

2
passes/fsm/fsm_detect.cc
View file

@ -225,7 +225,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
if (!warnings.empty()) {
string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", log_id(wire->module), log_id(wire));
for (auto w : warnings) warnmsg += " " + w;
log_warning("%s", warnmsg.c_str());
log_warning("%s", warnmsg);
} else {
log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire));
}

2
passes/hierarchy/hierarchy.cc
View file

@ -937,7 +937,7 @@ struct HierarchyPass : public Pass {
const std::string &value = args[++argidx];
auto r = parameters.emplace(key, value);
if (!r.second) {
log_warning("-chparam %s already specified: overwriting.\n", key.c_str());
log_warning("-chparam %s already specified: overwriting.\n", key);
r.first->second = value;
}
continue;

4
passes/hierarchy/submod.cc
View file

@ -95,7 +95,7 @@ struct SubmodWorker
for (auto &conn : cell->connections())
flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
} else {
log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type);
for (auto &conn : cell->connections())
flag_signal(conn.second, true, true, true, false, false);
}
@ -111,7 +111,7 @@ struct SubmodWorker
for (auto &conn : cell->connections())
flag_signal(conn.second, false, false, false, true, true);
if (flag_found_something)
log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type);
}
}

2
passes/memory/memlib.cc
View file

@ -1097,7 +1097,7 @@ Library MemLibrary::parse_library(const std::vector<std::string> &filenames, con
Parser(file, res, defines, defines_unused);
}
for (auto def: defines_unused) {
log_warning("define %s not used in the library.\n", def.c_str());
log_warning("define %s not used in the library.\n", def);
}
return res;
}

2
passes/opt/opt_clean.cc
View file

@ -233,7 +233,7 @@ void rmunused_module_cells(Module *module, bool verbose)
for (auto it : driver_driver_logs) {
if (used_raw_bits.count(it.first))
for (auto msg : it.second)
log_warning("%s\n", msg.c_str());
log_warning("%s\n", msg);
}
}

2
passes/sat/qbfsat.cc
View file

@ -233,7 +233,7 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt,
ret.stdout_lines.push_back(line.substr(0, line.size()-1)); //don't include trailing newline
auto warning_pos = line.find(smtbmc_warning);
if (warning_pos != std::string::npos)
log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str());
log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1));
else
if (opt.show_smtbmc && !quiet)
log("smtbmc output: %s", line);

24
passes/sat/sim.cc
View file

@ -256,7 +256,7 @@ struct SimInstance
if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0 && wire->name.isPublic())
log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)));
fst_handles[wire] = id;
}
@ -927,7 +927,7 @@ struct SimInstance
if (shared->serious_asserts)
log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
else
log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
log_warning("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
}
}
}
@ -1244,7 +1244,7 @@ struct SimInstance
Const fst_val = Const::from_string(shared->fst->valueOf(item.second));
Const sim_val = get_state(item.first);
if (sim_val.size()!=fst_val.size()) {
log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope.c_str(), log_id(item.first));
log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, log_id(item.first));
continue;
}
if (shared->sim_mode == SimulationMode::sim) {
@ -1252,7 +1252,7 @@ struct SimInstance
} else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
for(int i=0;i<fst_val.size();i++) {
if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
@ -1260,14 +1260,14 @@ struct SimInstance
} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
for(int i=0;i<sim_val.size();i++) {
if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation %s\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
break;
}
}
} else {
if (fst_val!=sim_val) {
log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope.c_str(), log_id(item.first), log_signal(fst_val), log_signal(sim_val));
log_warning("Signal '%s.%s' in file %s in simulation '%s'\n", scope, log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
}
}
@ -1607,7 +1607,7 @@ struct SimWorker : SimShared
escaped_s = RTLIL::escape_id(cell_name(symbol));
Cell *c = topmod->cell(escaped_s);
if (!c)
log_warning("Wire/cell %s not present in module %s\n",symbol.c_str(),log_id(topmod));
log_warning("Wire/cell %s not present in module %s\n",symbol,log_id(topmod));
if (c->is_mem_cell()) {
std::string memid = c->parameters.at(ID::MEMID).decode_string();
@ -1873,7 +1873,7 @@ struct SimWorker : SimShared
log("witness hierarchy: found wire %s\n", path.str());
bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second;
if (!inserted)
log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str());
}
} else if (item.mem) {
auto it = mem_paths.find(path);
@ -1890,7 +1890,7 @@ struct SimWorker : SimShared
continue;
bool inserted = hierarchy.paths.emplace(word_path, {instance, nullptr, item.mem->memid, addr}).second;
if (!inserted)
log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str());
}
}
}
@ -1899,7 +1899,7 @@ struct SimWorker : SimShared
for (auto &path : paths)
if (!hierarchy.paths.count(path))
log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str().c_str());
log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str());
dict<IdPath, dict<int, bool>> clock_inputs;
@ -1922,7 +1922,7 @@ struct SimWorker : SimShared
for (int t = 0; t < GetSize(yw.steps); t++) {
if (yw.get_bits(t, clock_bits_offset, 1) != expected)
log_warning("Yosys witness trace has an unexpected value for the clock input `%s` in step %d.\n", signal.path.str().c_str(), t);
log_warning("Yosys witness trace has an unexpected value for the clock input `%s` in step %d.\n", signal.path.str(), t);
}
}
}
@ -2000,7 +2000,7 @@ struct SimWorker : SimShared
YwHierarchy hierarchy = prepare_yw_hierarchy(yw);
if (yw.steps.empty()) {
log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str());
log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename);
} else {
top->set_initstate_outputs(initstate ? State::S1 : State::S0);
set_yw_state(yw, hierarchy, 0);

2
passes/techmap/abc9_exe.cc
View file

@ -329,7 +329,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
#endif
if (ret != 0) {
if (check_file_exists(stringf("%s/output.aig", tempdir_name)))
log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
else
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
}

4
passes/techmap/libparse.cc
View file

@ -191,7 +191,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) {
s.next();
lhs = parse(s);
if (s.peek() != ')') {
log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr().c_str());
log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr());
return lhs;
}
s.next();
@ -200,7 +200,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) {
lhs.kind = Kind::NOT;
lhs.children.push_back(parse(s, 7));
} else {
log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr().c_str());
log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr());
return lhs;
}

2
passes/tests/test_cell.cc
View file

@ -1192,7 +1192,7 @@ struct TestCellPass : public Pass {
worst_abs = num_cells - num_cells_estimate;
worst_rel = (float)(num_cells - num_cells_estimate) / (float)num_cells_estimate;
}
log_warning("Upper bound violated for %s: %d > %d\n", cell_type.c_str(), num_cells, num_cells_estimate);
log_warning("Upper bound violated for %s: %d > %d\n", cell_type, num_cells, num_cells_estimate);
}
}
}