From a7c46f7b4afc182af11b6f6ffb7a166d60fe7997 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 23:02:16 +0000 Subject: [PATCH] Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() --- backends/edif/edif.cc | 2 +- backends/firrtl/firrtl.cc | 6 +++--- frontends/ast/simplify.cc | 8 ++++---- frontends/verific/verific.cc | 4 ++-- frontends/verific/verificsva.cc | 2 +- kernel/log.cc | 4 ++-- kernel/register.cc | 2 +- kernel/tclapi.cc | 2 +- passes/cmds/check.cc | 6 +++--- passes/cmds/select.cc | 8 ++++---- passes/cmds/stat.cc | 4 ++-- passes/cmds/timeest.cc | 2 +- passes/equiv/equiv_add.cc | 8 ++++---- passes/fsm/fsm_detect.cc | 2 +- passes/hierarchy/hierarchy.cc | 2 +- passes/hierarchy/submod.cc | 4 ++-- passes/memory/memlib.cc | 2 +- passes/opt/opt_clean.cc | 2 +- passes/sat/qbfsat.cc | 2 +- passes/sat/sim.cc | 24 ++++++++++++------------ passes/techmap/abc9_exe.cc | 2 +- passes/techmap/libparse.cc | 4 ++-- passes/tests/test_cell.cc | 2 +- techlibs/intel/synth_intel.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 2 +- 25 files changed, 54 insertions(+), 54 deletions(-) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 83d0afaf3..d1be0b37f 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -513,7 +513,7 @@ struct EdifBackend : public Backend { if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) { if (sig == RTLIL::State::Sx) { for (auto &ref : it.second) - log_warning("Exporting x-bit on %s as zero bit.\n", ref.first.c_str()); + log_warning("Exporting x-bit on %s as zero bit.\n", ref.first); sig = RTLIL::State::S0; } else if (sig == RTLIL::State::Sz) { continue; diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index e54b46e63..577d95ad7 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -465,7 +465,7 @@ struct FirrtlWorker // If there is no instance for this, just return. if (instModule == NULL) { - log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str()); + log_warning("No instance for %s.%s\n", cell_type, cell_name); return; } @@ -490,7 +490,7 @@ struct FirrtlWorker const SigSpec *sinkSig = nullptr; switch (dir) { case FD_INOUT: - log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second)); + log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type, log_signal(it->second)); YS_FALLTHROUGH case FD_OUT: sourceExpr = firstName; @@ -498,7 +498,7 @@ struct FirrtlWorker sinkSig = &secondSig; break; case FD_NODIRECTION: - log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second)); + log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type, log_signal(it->second)); YS_FALLTHROUGH case FD_IN: sourceExpr = secondExpr; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 0df09030c..9b679d0aa 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -974,7 +974,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin message += stringf("%s%s", first_element ? " See " : ", ", place); first_element = false; } - log_warning("%s\n", message.c_str()); + log_warning("%s\n", message); } silent_activate: @@ -1144,7 +1144,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin i--; // Adjust index since we removed an element } else { // If we can't find the package, just remove the import node to avoid errors later - log_warning("Package `%s' not found for import, removing import statement\n", child->str.c_str()); + log_warning("Package `%s' not found for import, removing import statement\n", child->str); children.erase(children.begin() + i); i--; // Adjust index since we removed an element } @@ -1438,7 +1438,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic) children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg) - log_warning("wire '%s' is assigned in a block at %s.\n", children[0]->str.c_str(), loc_string().c_str()); + log_warning("wire '%s' is assigned in a block at %s.\n", children[0]->str, loc_string()); if (type == AST_ASSIGN && children[0]->id2ast->is_reg) { bool is_rand_reg = false; if (children[1]->type == AST_FCALL) { @@ -1452,7 +1452,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin is_rand_reg = true; } if (!is_rand_reg) - log_warning("reg '%s' is assigned in a continuous assignment at %s.\n", children[0]->str.c_str(), loc_string().c_str()); + log_warning("reg '%s' is assigned in a continuous assignment at %s.\n", children[0]->str, loc_string()); } children[0]->was_checked = true; } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 91af38ccd..279b0dd52 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -141,7 +141,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil #endif } else { if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) - log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); + log_warning_noprefix("%s%s\n", message_prefix, message); else log("%s%s\n", message_prefix, message); } @@ -4098,7 +4098,7 @@ struct VerificPass : public Pass { unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(), 1 /* force_overwrite */); if (!new_insertion) - log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str()); + log_warning_noprefix("-chparam %s already specified: overwriting.\n", key); continue; } if (args[argidx] == "-V") { diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index cc5f07004..3908947eb 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1025,7 +1025,7 @@ struct VerificSvaImporter { if (!importer->mode_keep) log_error("%s", errmsg); - log_warning("%s", errmsg.c_str()); + log_warning("%s", errmsg); throw ParserErrorException(); } diff --git a/kernel/log.cc b/kernel/log.cc index 3a44a3ddc..0085980b1 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -187,7 +187,7 @@ static void logv_string(std::string_view format, std::string str) { if (!linebuffer.empty() && linebuffer.back() == '\n') { for (auto &re : log_warn_regexes) if (std::regex_search(linebuffer, re)) - log_warning("Found log message matching -W regex:\n%s", str.c_str()); + log_warning("Found log message matching -W regex:\n%s", str); for (auto &[_, item] : log_expect_log) if (std::regex_search(linebuffer, item.pattern)) @@ -704,7 +704,7 @@ dict> get_coverage_data() for (auto &it : extra_coverage_data) { if (coverage_data.count(it.first)) - log_warning("found duplicate coverage id \"%s\".\n", it.first.c_str()); + log_warning("found duplicate coverage id \"%s\".\n", it.first); coverage_data[it.first].first = it.second.first; coverage_data[it.first].second += it.second.second; } diff --git a/kernel/register.cc b/kernel/register.cc index fe67cc35c..9436b540a 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -972,7 +972,7 @@ struct HelpPass : public Pass { } for (auto &it : cell_help_messages.cell_help) { if (cells.count(it.first) == 0) { - log_warning("Found cell model '%s' without matching cell type.\n", it.first.c_str()); + log_warning("Found cell model '%s' without matching cell type.\n", it.first); } } diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index 729d06ca0..a2ebaffa2 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -137,7 +137,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a if (err.empty()) { Tcl_SetObjResult(interp, json_to_tcl(interp, json)); } else - log_warning("Ignoring result.json scratchpad value due to parse error: %s\n", err.c_str()); + log_warning("Ignoring result.json scratchpad value due to parse error: %s\n", err); } else if ((result = scratchpad.find("result.string")) != scratchpad.end()) { Tcl_SetObjResult(interp, Tcl_NewStringObj(result->second.data(), result->second.size())); } diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index b532b4527..9f72d90f7 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -323,7 +323,7 @@ struct CheckPass : public Pass { string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state)); for (auto str : wire_drivers[state]) message += stringf(" %s\n", str); - log_warning("%s", message.c_str()); + log_warning("%s", message); counter++; } @@ -332,7 +332,7 @@ struct CheckPass : public Pass { string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first)); for (auto str : it.second) message += stringf(" %s\n", str); - log_warning("%s", message.c_str()); + log_warning("%s", message); counter++; } @@ -418,7 +418,7 @@ struct CheckPass : public Pass { prev = bit; } - log_warning("%s", message.c_str()); + log_warning("%s", message); counter++; } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 469e36ef1..6da15c19a 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -658,7 +658,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char } if (rem_objects == 0) - log_warning("reached configured limit at `%s'.\n", arg.c_str()); + log_warning("reached configured limit at `%s'.\n", arg); } static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel) @@ -1002,14 +1002,14 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp if (it.second == false && !disable_empty_warning) { std::string selection_str = select_blackboxes ? "=" : ""; selection_str += it.first; - log_warning("Selection \"%s\" did not match any module.\n", selection_str.c_str()); + log_warning("Selection \"%s\" did not match any module.\n", selection_str); } } for (auto &it : arg_memb_found) { if (it.second == false && !disable_empty_warning) { std::string selection_str = select_blackboxes ? "=" : ""; selection_str += it.first; - log_warning("Selection \"%s\" did not match any object.\n", selection_str.c_str()); + log_warning("Selection \"%s\" did not match any object.\n", selection_str); } } } @@ -1451,7 +1451,7 @@ struct SelectPass : public Pass { while (std::getline(f, line)) { size_t slash_pos = line.find('/'); if (slash_pos == string::npos) { - log_warning("Ignoring line without slash in 'select -read': %s\n", line.c_str()); + log_warning("Ignoring line without slash in 'select -read': %s\n", line); continue; } IdString mod_name = RTLIL::escape_id(line.substr(0, slash_pos)); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 6e46ab5e2..61135e066 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -228,7 +228,7 @@ struct statdata_t { cell_area.at(cell_type).is_sequential = cell_data.is_sequential; } else { - log_warning("too small single_parameter_area %s width: %d size: %d\n", cell_type.c_str(), max_width, + log_warning("too small single_parameter_area %s width: %d size: %d\n", cell_type, max_width, (int)cell_data.single_parameter_area.size()); cell_area.at(cell_type).area = cell_data.single_parameter_area.back(); cell_area.at(cell_type).is_sequential = cell_data.is_sequential; @@ -274,7 +274,7 @@ struct statdata_t { cell_data.double_parameter_area.at(width_a - 1).at(width_b - 1); cell_area.at(cell_type).is_sequential = cell_data.is_sequential; } else { - log_warning("too small double_parameter_area %s, width_a: %d, width_b: %d, size_a: %d, size_b: %d\n", cell_type.c_str(), + log_warning("too small double_parameter_area %s, width_a: %d, width_b: %d, size_a: %d, size_b: %d\n", cell_type, width_a, width_b, (int)cell_data.double_parameter_area.size(), (int)cell_data.double_parameter_area.at(width_a - 1).size()); cell_area.at(cell_type).area = cell_data.double_parameter_area.back().back(); diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index 86a529520..b878050da 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -403,7 +403,7 @@ struct TimeestPass : Pass { for (auto m : d->selected_modules()) { if (!m->wire(RTLIL::escape_id(clk))) { - log_warning("No domain '%s' in module %s\n", clk.c_str(), log_id(m)); + log_warning("No domain '%s' in module %s\n", clk, log_id(m)); continue; } diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 4deef6e32..b3c97fa80 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -61,7 +61,7 @@ struct EquivAddPass : public Pass { if (gold_cell == nullptr) { if (try_mode) { - log_warning("Can't find gold cell '%s'.\n", args[2].c_str()); + log_warning("Can't find gold cell '%s'.\n", args[2]); return; } log_cmd_error("Can't find gold cell '%s'.\n", args[2]); @@ -69,7 +69,7 @@ struct EquivAddPass : public Pass { if (gate_cell == nullptr) { if (try_mode) { - log_warning("Can't find gate cell '%s'.\n", args[3].c_str()); + log_warning("Can't find gate cell '%s'.\n", args[3]); return; } log_cmd_error("Can't find gate cell '%s'.\n", args[3]); @@ -126,7 +126,7 @@ struct EquivAddPass : public Pass { if (!SigSpec::parse(gate_signal, module, args[2])) { if (try_mode) { - log_warning("Error in gate signal: %s\n", args[2].c_str()); + log_warning("Error in gate signal: %s\n", args[2]); return; } log_cmd_error("Error in gate signal: %s\n", args[2]); @@ -134,7 +134,7 @@ struct EquivAddPass : public Pass { if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1])) { if (try_mode) { - log_warning("Error in gold signal: %s\n", args[1].c_str()); + log_warning("Error in gold signal: %s\n", args[1]); return; } log_cmd_error("Error in gold signal: %s\n", args[1]); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 86d654cc4..9cffbf95a 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -225,7 +225,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false) if (!warnings.empty()) { string warnmsg = stringf("Regarding the user-specified fsm_encoding attribute on %s.%s:\n", log_id(wire->module), log_id(wire)); for (auto w : warnings) warnmsg += " " + w; - log_warning("%s", warnmsg.c_str()); + log_warning("%s", warnmsg); } else { log("FSM state register %s.%s already has fsm_encoding attribute.\n", log_id(wire->module), log_id(wire)); } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index f670d1fd2..a7f86c3f0 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -937,7 +937,7 @@ struct HierarchyPass : public Pass { const std::string &value = args[++argidx]; auto r = parameters.emplace(key, value); if (!r.second) { - log_warning("-chparam %s already specified: overwriting.\n", key.c_str()); + log_warning("-chparam %s already specified: overwriting.\n", key); r.first->second = value; } continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index f979e7acc..bf135386c 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -95,7 +95,7 @@ struct SubmodWorker for (auto &conn : cell->connections()) flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); } else { - log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); + log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type); for (auto &conn : cell->connections()) flag_signal(conn.second, true, true, true, false, false); } @@ -111,7 +111,7 @@ struct SubmodWorker for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, true, true); if (flag_found_something) - log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); + log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name, cell->type); } } diff --git a/passes/memory/memlib.cc b/passes/memory/memlib.cc index 216b750fd..11c9f9074 100644 --- a/passes/memory/memlib.cc +++ b/passes/memory/memlib.cc @@ -1097,7 +1097,7 @@ Library MemLibrary::parse_library(const std::vector &filenames, con Parser(file, res, defines, defines_unused); } for (auto def: defines_unused) { - log_warning("define %s not used in the library.\n", def.c_str()); + log_warning("define %s not used in the library.\n", def); } return res; } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index cef2c0dc3..b9df09ea6 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -233,7 +233,7 @@ void rmunused_module_cells(Module *module, bool verbose) for (auto it : driver_driver_logs) { if (used_raw_bits.count(it.first)) for (auto msg : it.second) - log_warning("%s\n", msg.c_str()); + log_warning("%s\n", msg); } } diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index ad28884f7..b011227e2 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -233,7 +233,7 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt, ret.stdout_lines.push_back(line.substr(0, line.size()-1)); //don't include trailing newline auto warning_pos = line.find(smtbmc_warning); if (warning_pos != std::string::npos) - log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str()); + log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1)); else if (opt.show_smtbmc && !quiet) log("smtbmc output: %s", line); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 56b207a58..1b653a218 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -256,7 +256,7 @@ struct SimInstance if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) { fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); if (id==0 && wire->name.isPublic()) - log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str()); + log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name))); fst_handles[wire] = id; } @@ -927,7 +927,7 @@ struct SimInstance if (shared->serious_asserts) log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label); else - log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log_warning("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label); } } } @@ -1244,7 +1244,7 @@ struct SimInstance Const fst_val = Const::from_string(shared->fst->valueOf(item.second)); Const sim_val = get_state(item.first); if (sim_val.size()!=fst_val.size()) { - log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope.c_str(), log_id(item.first)); + log_warning("Signal '%s.%s' size is different in gold and gate.\n", scope, log_id(item.first)); continue; } if (shared->sim_mode == SimulationMode::sim) { @@ -1252,7 +1252,7 @@ struct SimInstance } else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X for(int i=0;isim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X for(int i=0;icell(escaped_s); if (!c) - log_warning("Wire/cell %s not present in module %s\n",symbol.c_str(),log_id(topmod)); + log_warning("Wire/cell %s not present in module %s\n",symbol,log_id(topmod)); if (c->is_mem_cell()) { std::string memid = c->parameters.at(ID::MEMID).decode_string(); @@ -1873,7 +1873,7 @@ struct SimWorker : SimShared log("witness hierarchy: found wire %s\n", path.str()); bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second; if (!inserted) - log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str()); + log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str()); } } else if (item.mem) { auto it = mem_paths.find(path); @@ -1890,7 +1890,7 @@ struct SimWorker : SimShared continue; bool inserted = hierarchy.paths.emplace(word_path, {instance, nullptr, item.mem->memid, addr}).second; if (!inserted) - log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str()); + log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str()); } } } @@ -1899,7 +1899,7 @@ struct SimWorker : SimShared for (auto &path : paths) if (!hierarchy.paths.count(path)) - log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str().c_str()); + log_warning("Yosys witness path `%s` was not found in this design, ignoring\n", path.str()); dict> clock_inputs; @@ -1922,7 +1922,7 @@ struct SimWorker : SimShared for (int t = 0; t < GetSize(yw.steps); t++) { if (yw.get_bits(t, clock_bits_offset, 1) != expected) - log_warning("Yosys witness trace has an unexpected value for the clock input `%s` in step %d.\n", signal.path.str().c_str(), t); + log_warning("Yosys witness trace has an unexpected value for the clock input `%s` in step %d.\n", signal.path.str(), t); } } } @@ -2000,7 +2000,7 @@ struct SimWorker : SimShared YwHierarchy hierarchy = prepare_yw_hierarchy(yw); if (yw.steps.empty()) { - log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str()); + log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename); } else { top->set_initstate_outputs(initstate ? State::S1 : State::S0); set_yw_state(yw, hierarchy, 0); diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index d7a7e3d4a..ac723fdbb 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -329,7 +329,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe #endif if (ret != 0) { if (check_file_exists(stringf("%s/output.aig", tempdir_name))) - log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); + log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); else log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); } diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index c89495c62..7d4fd77ad 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -191,7 +191,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) { s.next(); lhs = parse(s); if (s.peek() != ')') { - log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr().c_str()); + log_warning("expected ')' instead of '%c' while parsing Liberty expression '%s'\n", s.peek(), s.full_expr()); return lhs; } s.next(); @@ -200,7 +200,7 @@ LibertyExpression LibertyExpression::parse(Lexer &s, int min_prio) { lhs.kind = Kind::NOT; lhs.children.push_back(parse(s, 7)); } else { - log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr().c_str()); + log_warning("unrecognised character '%c' while parsing Liberty expression '%s'\n", c, s.full_expr()); return lhs; } diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index f882aa356..9603956a8 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -1192,7 +1192,7 @@ struct TestCellPass : public Pass { worst_abs = num_cells - num_cells_estimate; worst_rel = (float)(num_cells - num_cells_estimate) / (float)num_cells_estimate; } - log_warning("Upper bound violated for %s: %d > %d\n", cell_type.c_str(), num_cells, num_cells_estimate); + log_warning("Upper bound violated for %s: %d > %d\n", cell_type, num_cells, num_cells_estimate); } } } diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index d3202d5cb..e02885cd0 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -242,7 +242,7 @@ struct SynthIntelPass : public ScriptPass { run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)"); run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)"); } else { - log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str()); + log_warning("BRAM mapping is not currently supported for %s.\n", family_opt); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 20b8c98c3..46b30573c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -316,7 +316,7 @@ struct SynthXilinxPass : public ScriptPass log_cmd_error("-widemux is not currently supported for LUT4-based architectures.\n"); if (lut_size != 6) { - log_warning("Shift register inference not yet supported for family %s.\n", family.c_str()); + log_warning("Shift register inference not yet supported for family %s.\n", family); nosrl = true; }