Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort

write_rtlil: don't sort

tests/bugpoint/raise_error.ys

@@ -22,34 +22,37 @@ logger -check-expected
 
 # raise_error with int exits with status
 design -load read
+setattr -mod -unset raise_error def other
+dump
 bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7
 select -assert-mod-count 1 =*
 select -assert-mod-count 1 top
 
 # raise_error -always still uses 'raise_error' attribute if possible
 design -load read
+setattr -mod -unset raise_error def other
 bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7
 select -assert-mod-count 1 =*
 select -assert-mod-count 1 top
 
 # raise_error with string prints message and exits with 1
 design -load read
-rename top abc
+setattr -mod -unset raise_error top def
 bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1
 select -assert-mod-count 1 =*
 select -assert-mod-count 1 other
 
 # raise_error with no value exits with 1
 design -load read
-rename def zzy
+setattr -mod -unset raise_error top
 delete other
 bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1
 select -assert-mod-count 1 =*
-select -assert-mod-count 1 zzy
+select -assert-mod-count 1 def
 
 # raise_error -stderr prints to stderr and exits with 1
 design -load read
-rename top abc
+setattr -mod -unset raise_error top def
 bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1
 select -assert-mod-count 1 =*
 select -assert-mod-count 1 other

tests/functional/test_functional.py

@@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args):
     run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
 
 def yosys_synth(verilog_file, rtlil_file):
-    yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}")
+    yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven -undef ; write_rtlil {quote(rtlil_file)}")
 
 # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
 def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
@@ -91,4 +91,4 @@ def test_print_graph(tmp_path):
     tb_file = base_path / 'tests/functional/picorv32_tb.v'
     cpu_file = base_path / 'tests/functional/picorv32.v'
     # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl
-    yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic")
+    yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven -undef ; flatten; clk2fflogic; test_generic")

tests/rtlil/.gitignore

@@ -0,0 +1 @@
+/temp

tests/rtlil/everything.v

@@ -0,0 +1,40 @@
+module alu(
+	input clk,
+	input [7:0] A,
+	input [7:0] B,
+	input [3:0] operation,
+	output reg [7:0] result,
+	output reg CF,
+	output reg ZF,
+	output reg SF
+);
+
+	localparam ALU_OP_ADD = 4'b0000;
+	localparam ALU_OP_SUB = 4'b0001;
+
+	reg [8:0] tmp;
+
+	always @(posedge clk)
+	begin
+		case (operation)
+			ALU_OP_ADD :
+				tmp = A + B;
+			ALU_OP_SUB :
+				tmp = A - B;
+		endcase
+
+		CF <= tmp[8];
+		ZF <= tmp[7:0] == 0;
+		SF <= tmp[7];
+
+		result <= tmp[7:0];
+	end
+endmodule
+
+module foo(
+    input [7:0] a, input [7:0] b, output [7:0] y
+);
+    wire [7:0] bb;
+    assign b = bb;
+    assign y = a + bb;
+endmodule

tests/rtlil/roundtrip-design.sh

@@ -0,0 +1,10 @@
+set -euo pipefail
+YS=../../yosys
+
+mkdir -p temp
+
+$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il"
+diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il
+
+$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il"
+diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il

tests/rtlil/roundtrip-text.sh

@@ -0,0 +1,31 @@
+set -euo pipefail
+YS=../../yosys
+
+mkdir -p temp
+
+# non-POSIX sed -i inconsistency workaround
+remove_empty_lines() {
+    local file="$1"
+    sed '/^$/d' "$file" > temp/tmp
+    mv temp/tmp "$file"
+}
+
+# write_rtlil and dump are equivalent
+$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il"
+remove_empty_lines temp/roundtrip-text.dump.il
+remove_empty_lines temp/roundtrip-text.write.il
+# Trim first line ("Generated by Yosys ...")
+tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il
+diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il
+
+# Loading and writing it out again doesn't change the RTLIL
+$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il"
+remove_empty_lines temp/roundtrip-text.reload.il
+tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il
+diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il
+
+# Hashing differences don't change the RTLIL
+$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il"
+remove_empty_lines temp/roundtrip-text.reload-hash.il
+tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il
+diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il

tests/rtlil/run-test.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../gen-tests-makefile.sh
+generate_mk --bash