mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-22 05:36:43 +00:00
Code Activity

fsm_detect: fix test

Browse source
This commit is contained in:
Anhijkt 2025-11-14 13:25:51 +02:00
parent 7d10a72490
commit a75b999f13
1 changed files with 10 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

28
tests/various/fsm-arst.ys
View file

@ -33,7 +33,6 @@ endmodule
module semi_self_rs_fsm (
input wire clk,
inout wire reset,
input wire test,
output wire s1
);
@ -44,7 +43,7 @@ module semi_self_rs_fsm (
reg [7:0] current_state, next_state;
reg [1:0] reset_test;
assign reset = (test || (reset_test == 2));
wire reset = (test || (reset_test == 2));
always @(posedge clk or posedge reset) begin
if (reset) begin
@ -75,39 +74,28 @@ endmodule
module self_rs_fsm (
input wire clk,
inout wire reset,
output wire s1
);
localparam [7:0] RST = 8'b10010010;
localparam [7:0] S1 = 8'b01001000;
localparam [7:0] S2 = 8'b11000111;
reg [7:0] current_state, next_state;
reg reset_reg;
reg [7:0] next_state;
wire reset = (reset_reg || next_state == S1);
always @(posedge clk or posedge reset) begin
if (reset) begin
current_state <= RST;
reset_reg = 0;
next_state <= RST;
end else begin
current_state <= next_state;
end
end
always @(*) begin
next_state = current_state;
case (current_state)
case (next_state)
RST: next_state = S1;
S1: next_state = S2;
S2: next_state = S1;
default: begin
reset_reg = 1;
next_state = RST;
end
default: next_state = RST;
endcase
end
end
assign s1 = next_state == S1;
endmodule