From a75b999f133b90c35f366e6b170ad03b3fda796a Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Fri, 14 Nov 2025 13:25:51 +0200
Subject: [PATCH] fsm_detect: fix test

---
 tests/various/fsm-arst.ys | 32 ++++++++++----------------------
 1 file changed, 10 insertions(+), 22 deletions(-)

diff --git a/tests/various/fsm-arst.ys b/tests/various/fsm-arst.ys
index 2cfca1d57..d3c40444b 100644
--- a/tests/various/fsm-arst.ys
+++ b/tests/various/fsm-arst.ys
@@ -33,7 +33,6 @@ endmodule
 
 module semi_self_rs_fsm (
     input  wire clk,
-    inout  wire reset,
     input wire test,
     output wire s1
 );
@@ -44,7 +43,7 @@ module semi_self_rs_fsm (
     reg [7:0] current_state, next_state;
     reg [1:0] reset_test;
 
-    assign reset = (test || (reset_test == 2));
+    wire reset = (test || (reset_test == 2));
 
     always @(posedge clk or posedge reset) begin
         if (reset) begin
@@ -75,39 +74,28 @@ endmodule
 
 module self_rs_fsm (
     input  wire clk,
-    inout  wire reset,
     output wire s1
 );
     localparam [7:0] RST = 8'b10010010;
     localparam [7:0] S1 = 8'b01001000;
     localparam [7:0] S2 = 8'b11000111;
 
-    reg [7:0] current_state, next_state;
-    reg reset_reg;
-
+    reg [7:0] next_state;
     wire reset = (reset_reg || next_state == S1);
+
     always @(posedge clk or posedge reset) begin
         if (reset) begin
-            current_state <= RST;
-            reset_reg = 0;
+            next_state <= RST;
         end else begin
-            current_state <= next_state;
+            case (next_state)
+                RST: next_state = S1;
+                S1: next_state = S2;
+                S2: next_state = S1;
+                default: next_state = RST;
+            endcase
         end
     end
 
-    always @(*) begin
-        next_state = current_state;
-
-        case (current_state)
-            RST: next_state = S1;
-            S1: next_state = S2;
-            S2: next_state = S1;
-            default: begin 
-                reset_reg = 1;
-                next_state = RST;
-            end
-        endcase
-    end
 
     assign s1 = next_state == S1;
 endmodule