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fsm_detect: fix test

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Anhijkt 2025-11-14 13:25:51 +02:00
parent 7d10a72490
commit a75b999f13
1 changed files with 10 additions and 22 deletions
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32
tests/various/fsm-arst.ys
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@ -33,7 +33,6 @@ endmodule
module semi_self_rs_fsm ( module semi_self_rs_fsm (
input wire clk, input wire clk,
inout wire reset,
input wire test, input wire test,
output wire s1 output wire s1
); );
@ -44,7 +43,7 @@ module semi_self_rs_fsm (
reg [7:0] current_state, next_state; reg [7:0] current_state, next_state;
reg [1:0] reset_test; reg [1:0] reset_test;
assign reset = (test || (reset_test == 2)); wire reset = (test || (reset_test == 2));
always @(posedge clk or posedge reset) begin always @(posedge clk or posedge reset) begin
if (reset) begin if (reset) begin
@ -75,39 +74,28 @@ endmodule
module self_rs_fsm ( module self_rs_fsm (
input wire clk, input wire clk,
inout wire reset,
output wire s1 output wire s1
); );
localparam [7:0] RST = 8'b10010010; localparam [7:0] RST = 8'b10010010;
localparam [7:0] S1 = 8'b01001000; localparam [7:0] S1 = 8'b01001000;
localparam [7:0] S2 = 8'b11000111; localparam [7:0] S2 = 8'b11000111;
reg [7:0] current_state, next_state; reg [7:0] next_state;
reg reset_reg;
wire reset = (reset_reg || next_state == S1); wire reset = (reset_reg || next_state == S1);
always @(posedge clk or posedge reset) begin always @(posedge clk or posedge reset) begin
if (reset) begin if (reset) begin
current_state <= RST; next_state <= RST;
reset_reg = 0;
end else begin end else begin
current_state <= next_state; case (next_state)
RST: next_state = S1;
S1: next_state = S2;
S2: next_state = S1;
default: next_state = RST;
endcase
end end
end end
always @(*) begin
next_state = current_state;
case (current_state)
RST: next_state = S1;
S1: next_state = S2;
S2: next_state = S1;
default: begin
reset_reg = 1;
next_state = RST;
end
endcase
end
assign s1 = next_state == S1; assign s1 = next_state == S1;
endmodule endmodule