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Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram

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xilinx: add LUTRAM rules for RAM32M, RAM64M
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Eddie Hung 2019-12-16 21:48:21 -08:00 • committed by GitHub
commit a73f96594f
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13 changed files with 529 additions and 65 deletions
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42
tests/arch/common/lutram.v Normal file
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module lutram_1w1r
#(parameter D_WIDTH=8, A_WIDTH=6)
(
input [D_WIDTH-1:0] data_a,
input [A_WIDTH:1] addr_a,
input we_a, clk,
output reg [D_WIDTH-1:0] q_a
);
// Declare the RAM variable
reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
ram[addr_a] <= data_a;
q_a <= ram[addr_a];
end
endmodule
module lutram_1w3r
#(parameter D_WIDTH=8, A_WIDTH=5)
(
input [D_WIDTH-1:0] data_a, data_b, data_c,
input [A_WIDTH:1] addr_a, addr_b, addr_c,
input we_a, clk,
output reg [D_WIDTH-1:0] q_a, q_b, q_c
);
// Declare the RAM variable
reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
ram[addr_a] <= data_a;
q_a <= ram[addr_a];
q_b <= ram[addr_b];
q_c <= ram[addr_c];
end
endmodule

21
tests/arch/common/memory.v
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module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule