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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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2
tests/verilog/param_default.ys
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@ -5,7 +5,7 @@ module bar (
);
parameter paramname = 7;
endmodule
module empty (
);
bar #() barinstance ();

2
tests/verilog/string-literals.ys
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@ -41,7 +41,7 @@ module top;
wire[7:0] dig8val = 56;
wire[7:0] dig9 = "\9"; // not octal, a literal '9'
wire[7:0] dig9val = 57;
wire[7:0] cl = "\:";
wire[7:0] clval = 58;
wire[7:0] sc = "\;";