From a6893422070da115bc19b0ff1c9efe5367f29088 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 23 Jun 2026 07:24:59 +0200 Subject: [PATCH] Remove trailing whitespaces --- CHANGELOG | 44 +- backends/aiger/xaiger.cc | 2 +- backends/functional/smtlib.cc | 6 +- backends/functional/smtlib_rosette.cc | 2 +- backends/functional/test_generic.cc | 2 +- backends/smt2/ywio.py | 4 +- cmake/YosysAbc.cmake | 6 +- .../appendix/APPNOTE_010_Verilog_to_BLIF.rst | 6 +- .../appendix/APPNOTE_012_Verilog_to_BTOR.rst | 2 +- docs/source/appendix/primer.rst | 4 +- docs/source/appendix/rtlil_text.rst | 32 +- docs/source/cell/word_logic.rst | 2 +- docs/source/cmd/index_internal.rst | 6 +- docs/source/code_examples/fifo/Makefile | 2 +- docs/source/code_examples/fifo/fifo.v | 4 +- docs/source/code_examples/fifo/fifo.ys | 2 +- .../macro_commands/synth_ice40.ys | 4 +- docs/source/code_examples/opt/opt_expr.ys | 2 +- docs/source/code_examples/opt/opt_muxtree.ys | 2 +- docs/source/code_examples/show/cmos.ys | 4 +- docs/source/getting_started/example_synth.rst | 12 +- docs/source/getting_started/installation.rst | 2 +- .../getting_started/scripting_intro.rst | 4 +- docs/source/introduction.rst | 22 +- docs/source/literature.bib | 66 +- .../interactive_investigation.rst | 32 +- .../more_scripting/load_design.rst | 2 +- .../using_yosys/more_scripting/selections.rst | 20 +- .../using_yosys/synthesis/cell_libs.rst | 4 +- docs/source/using_yosys/synthesis/extract.rst | 4 +- docs/source/using_yosys/synthesis/fsm.rst | 2 +- docs/source/using_yosys/synthesis/memory.rst | 12 +- .../using_yosys/synthesis/techmap_synth.rst | 2 +- .../extending_yosys/advanced_bugpoint.rst | 2 +- .../extending_yosys/extensions.rst | 2 +- docs/source/yosys_internals/flow/index.rst | 2 +- .../yosys_internals/flow/verilog_frontend.rst | 10 +- docs/source/yosys_internals/formats/index.rst | 2 +- docs/tests/macro_commands.py | 2 +- docs/util/RtlilLexer.py | 2 +- docs/util/cell_documenter.py | 28 +- docs/util/cmd_documenter.py | 18 +- docs/util/custom_directives.py | 30 +- examples/intel/asicworld_lfsr/lfsr_updown.v | 6 +- .../intel/asicworld_lfsr/lfsr_updown_tb.v | 2 +- examples/smtbmc/glift/C7552.v | 838 ++++---- examples/smtbmc/glift/C7552.ys | 2 +- examples/smtbmc/glift/C880.v | 98 +- examples/smtbmc/glift/C880.ys | 2 +- examples/smtbmc/glift/alu2.v | 66 +- examples/smtbmc/glift/alu2.ys | 2 +- examples/smtbmc/glift/alu4.v | 142 +- examples/smtbmc/glift/alu4.ys | 2 +- examples/smtbmc/glift/t481.v | 12 +- examples/smtbmc/glift/t481.ys | 2 +- examples/smtbmc/glift/too_large.v | 68 +- examples/smtbmc/glift/too_large.ys | 2 +- examples/smtbmc/glift/ttt2.v | 44 +- examples/smtbmc/glift/ttt2.ys | 2 +- examples/smtbmc/glift/x1.v | 86 +- examples/smtbmc/glift/x1.ys | 2 +- frontends/verific/verific.cc | 34 +- kernel/cellhelp.py | 4 +- kernel/compressor_tree.cc | 2 +- kernel/functional.h | 8 +- kernel/io.h | 6 +- kernel/tclapi.cc | 2 +- kernel/topo_scc.h | 2 +- passes/cmds/check.cc | 6 +- passes/cmds/linecoverage.cc | 4 +- passes/cmds/linux_perf.cc | 2 +- passes/cmds/logger.cc | 6 +- passes/cmds/select.cc | 2 +- passes/cmds/setenv.cc | 4 +- passes/cmds/timeest.cc | 6 +- passes/memory/memory_libmap.cc | 4 +- passes/opt/muxpack.cc | 2 +- passes/opt/opt_balance_tree.cc | 32 +- passes/opt/opt_hier.cc | 4 +- passes/opt/opt_lut.cc | 2 +- passes/opt/opt_share.cc | 2 +- passes/opt/peepopt_muldiv_c.pmg | 8 +- passes/opt/peepopt_shiftadd.pmg | 4 +- passes/sat/cutpoint.cc | 2 +- passes/sat/qbfsat.h | 2 +- passes/sat/sim.cc | 48 +- passes/sat/synthprop.cc | 2 +- passes/techmap/abc9.cc | 2 +- passes/techmap/abc_new.cc | 2 +- passes/techmap/booth.cc | 4 +- passes/techmap/dfflegalize.cc | 2 +- passes/techmap/extract_counter.cc | 4 +- passes/techmap/libparse.cc | 4 +- passes/techmap/lut2mux.cc | 6 +- passes/techmap/techmap.cc | 2 +- techlibs/analogdevices/cells_sim.v | 4 +- techlibs/anlogic/anlogic_fixcarry.cc | 16 +- techlibs/anlogic/arith_map.v | 4 +- techlibs/anlogic/cells_sim.v | 10 +- techlibs/anlogic/eagle_bb.v | 24 +- techlibs/common/mul2dsp.v | 4 +- techlibs/common/simlib.v | 16 +- techlibs/efinix/arith_map.v | 6 +- techlibs/efinix/brams_map.v | 4 +- techlibs/efinix/cells_sim.v | 28 +- techlibs/efinix/efinix_fixcarry.cc | 14 +- techlibs/fabulous/prims.v | 26 +- techlibs/fix_mod.py | 2 +- techlibs/gatemate/gatemate_foldinv.cc | 2 +- techlibs/gowin/cells_sim.v | 24 +- techlibs/gowin/cells_xtra_gw1n.v | 228 +- techlibs/gowin/cells_xtra_gw2a.v | 266 +-- techlibs/gowin/cells_xtra_gw5a.v | 1836 ++++++++--------- techlibs/ice40/ice40_dsp.pmg | 4 +- techlibs/intel_alm/common/abc9_map.v | 4 +- techlibs/intel_alm/common/megafunction_bb.v | 82 +- techlibs/lattice/cells_sim_nexus.v | 4 +- techlibs/lattice/dsp_map_nexus.v | 6 +- techlibs/lattice/lattice_dsp_nexus.cc | 4 +- techlibs/lattice/lattice_dsp_nexus.pmg | 8 +- techlibs/lattice/lattice_gsr.cc | 4 +- techlibs/microchip/LSRAM.txt | 36 +- techlibs/microchip/LSRAM_map.v | 16 +- techlibs/microchip/arith_map.v | 2 +- techlibs/microchip/cells_sim.v | 14 +- techlibs/microchip/microchip_dsp.pmg | 24 +- techlibs/microchip/microchip_dsp_CREG.pmg | 6 +- techlibs/microchip/microchip_dsp_cascade.pmg | 18 +- techlibs/microchip/polarfire_dsp_map.v | 10 +- techlibs/microchip/uSRAM.txt | 12 +- techlibs/microchip/uSRAM_map.v | 4 +- techlibs/nanoxplore/brams_init.vh | 2 +- techlibs/nanoxplore/cells_sim_u.v | 8 +- techlibs/nanoxplore/nx_carry.cc | 8 +- techlibs/nanoxplore/rf_rams_map_l.v | 2 +- techlibs/nanoxplore/rf_rams_map_m.v | 2 +- techlibs/nanoxplore/synth_nanoxplore.cc | 6 +- techlibs/quicklogic/pp3/abc9_map.v | 4 +- techlibs/quicklogic/ql_bram_merge.cc | 2 +- techlibs/quicklogic/ql_bram_types.cc | 6 +- .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 2 +- techlibs/quicklogic/synth_quicklogic.cc | 2 +- techlibs/sf2/NOTES.txt | 4 +- techlibs/xilinx/tests/test_dsp_model.v | 2 +- .../analogdevices/asym_ram_sdp_read_wider.v | 2 +- tests/arch/analogdevices/attributes_test.ys | 8 +- tests/arch/analogdevices/blockram.ys | 4 +- tests/arch/analogdevices/bug1598.ys | 6 +- tests/arch/analogdevices/dsp_abc9.ys | 4 +- tests/arch/common/blockram.v | 2 +- tests/arch/common/fsm.v | 2 +- tests/arch/common/shifter.v | 2 +- tests/arch/ecp5/bug1598.ys | 4 +- tests/arch/ecp5/memories.ys | 2 +- tests/arch/ecp5/shifter.ys | 2 +- tests/arch/ice40/bug1598.ys | 4 +- tests/arch/ice40/bug1626.ys | 8 +- tests/arch/ice40/ice40_dsp_const.ys | 6 +- tests/arch/ice40/spram.v | 2 +- tests/arch/microchip/dff.ys | 6 +- tests/arch/microchip/dff_opt.ys | 6 +- tests/arch/microchip/dsp.ys | 8 +- tests/arch/microchip/mult.ys | 6 +- tests/arch/microchip/ram_SDP.ys | 8 +- tests/arch/microchip/ram_TDP.ys | 8 +- tests/arch/microchip/reduce.ys | 6 +- tests/arch/microchip/simple_ram.ys | 6 +- tests/arch/microchip/uram_ar.ys | 8 +- tests/arch/microchip/uram_sr.ys | 8 +- tests/arch/microchip/widemux.ys | 6 +- tests/arch/nanoxplore/meminit.v | 2 +- tests/arch/nanoxplore/meminit.ys | 6 +- tests/arch/quicklogic/qlf_k6n10f/dffs.ys | 4 +- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 4 +- tests/arch/quicklogic/qlf_k6n10f/meminit.v | 2 +- tests/arch/xilinx/asym_ram_sdp_read_wider.v | 2 +- tests/arch/xilinx/attributes_test.ys | 8 +- tests/arch/xilinx/blockram.ys | 4 +- tests/arch/xilinx/bug1598.ys | 4 +- tests/arch/xilinx/xilinx_srl.v | 2 +- tests/asicworld/code_hdl_models_GrayCounter.v | 10 +- tests/asicworld/code_hdl_models_arbiter.v | 60 +- tests/asicworld/code_hdl_models_arbiter_tb.v | 30 +- tests/asicworld/code_hdl_models_cam.v | 16 +- tests/asicworld/code_hdl_models_clk_div.v | 12 +- tests/asicworld/code_hdl_models_clk_div_45.v | 4 +- .../code_hdl_models_decoder_using_assign.v | 10 +- .../code_hdl_models_dff_async_reset.v | 4 +- .../code_hdl_models_dff_sync_reset.v | 2 +- .../code_hdl_models_encoder_using_case.v | 34 +- .../code_hdl_models_encoder_using_if.v | 66 +- .../asicworld/code_hdl_models_gray_counter.v | 26 +- tests/asicworld/code_hdl_models_lfsr.v | 2 +- tests/asicworld/code_hdl_models_lfsr_updown.v | 8 +- .../code_hdl_models_mux_using_case.v | 4 +- tests/asicworld/code_hdl_models_one_hot_cnt.v | 4 +- .../asicworld/code_hdl_models_parallel_crc.v | 4 +- .../code_hdl_models_parity_using_assign.v | 14 +- .../code_hdl_models_parity_using_bitwise.v | 6 +- .../code_hdl_models_parity_using_function.v | 22 +- ...code_hdl_models_pri_encoder_using_assign.v | 42 +- .../code_hdl_models_rom_using_case.v | 4 +- tests/asicworld/code_hdl_models_serial_crc.v | 6 +- .../code_hdl_models_tff_async_reset.v | 2 +- .../code_hdl_models_tff_sync_reset.v | 2 +- tests/asicworld/code_hdl_models_uart.v | 14 +- tests/asicworld/code_hdl_models_up_counter.v | 2 +- .../code_hdl_models_up_counter_load.v | 6 +- .../code_hdl_models_up_down_counter.v | 4 +- tests/asicworld/code_specman_switch_fabric.v | 22 +- tests/asicworld/code_tidbits_asyn_reset.v | 8 +- tests/asicworld/code_tidbits_blocking.v | 6 +- .../asicworld/code_tidbits_fsm_using_always.v | 2 +- .../code_tidbits_fsm_using_function.v | 4 +- .../code_tidbits_fsm_using_single_always.v | 2 +- tests/asicworld/code_tidbits_nonblocking.v | 6 +- .../code_tidbits_reg_combo_example.v | 2 +- .../asicworld/code_tidbits_reg_seq_example.v | 2 +- tests/asicworld/code_tidbits_syn_reset.v | 14 +- .../code_verilog_tutorial_always_example.v | 2 +- .../asicworld/code_verilog_tutorial_bus_con.v | 4 +- .../asicworld/code_verilog_tutorial_comment.v | 4 +- .../asicworld/code_verilog_tutorial_counter.v | 4 +- tests/asicworld/code_verilog_tutorial_d_ff.v | 2 +- .../asicworld/code_verilog_tutorial_decoder.v | 16 +- .../code_verilog_tutorial_decoder_always.v | 4 +- .../code_verilog_tutorial_escape_id.v | 2 +- .../code_verilog_tutorial_explicit.v | 2 +- .../code_verilog_tutorial_first_counter.v | 2 +- .../code_verilog_tutorial_first_counter_tb.v | 8 +- .../code_verilog_tutorial_flip_flop.v | 4 +- .../code_verilog_tutorial_fsm_full.v | 8 +- .../code_verilog_tutorial_fsm_full_tb.v | 4 +- .../code_verilog_tutorial_multiply.v | 4 +- .../asicworld/code_verilog_tutorial_mux_21.v | 4 +- .../code_verilog_tutorial_n_out_primitive.v | 6 +- .../code_verilog_tutorial_parallel_if.v | 6 +- .../asicworld/code_verilog_tutorial_parity.v | 4 +- .../code_verilog_tutorial_simple_if.v | 2 +- .../asicworld/code_verilog_tutorial_tri_buf.v | 4 +- .../code_verilog_tutorial_which_clock.v | 2 +- tests/bugpoint/procs.il | 8 +- tests/cxxrtl/test_value_fuzz.cc | 12 +- tests/functional/README.md | 4 +- tests/functional/rkt_vcd.py | 8 +- tests/functional/smt_vcd.py | 14 +- tests/hana/hana_vlib.v | 204 +- tests/hana/test_intermout.v | 50 +- tests/hana/test_parse2synthtrans.v | 2 +- tests/hana/test_simulation_always.v | 22 +- tests/hana/test_simulation_decoder.v | 12 +- tests/hana/test_simulation_mux.v | 8 +- tests/hana/test_simulation_seq.v | 4 +- tests/hana/test_simulation_sop.v | 4 +- tests/hana/test_simulation_techmap.v | 2 +- tests/hana/test_simulation_vlib.v | 4 +- tests/liberty/busdef.lib | 14 +- tests/liberty/dff.lib | 4 +- tests/liberty/issue3498_bad.lib | 8 +- tests/liberty/normal.lib | 72 +- tests/liberty/processdefs.lib | 6 +- tests/liberty/semicolextra.lib | 2 +- tests/liberty/semicolmissing.lib | 20 +- tests/liberty/small.v | 2 +- tests/memlib/memlib_9b1B.txt | 2 +- tests/memlib/memlib_9b1B.v | 2 +- tests/memlib/memlib_block_sp.v | 4 +- tests/memlib/memlib_block_sp_full.v | 4 +- tests/memories/issue00335.v | 10 +- tests/opt/opt_balance_tree.ys | 34 +- tests/pass-fuzzing.md | 4 +- tests/sat/grom.ys | 2 +- tests/sat/grom_cpu.v | 6 +- tests/sdc/alu_sub.sdc | 2 +- tests/sim/generate_mk.py | 2 +- tests/sim/tb/tb_adff.v | 2 +- tests/sim/tb/tb_adffe.v | 2 +- tests/sim/tb/tb_adlatch.v | 2 +- tests/sim/tb/tb_aldff.v | 2 +- tests/sim/tb/tb_aldffe.v | 2 +- tests/sim/tb/tb_dff.v | 2 +- tests/sim/tb/tb_dffe.v | 2 +- tests/sim/tb/tb_dffsr.v | 2 +- tests/sim/tb/tb_dlatch.v | 2 +- tests/sim/tb/tb_dlatchsr.v | 2 +- tests/sim/tb/tb_sdff.v | 2 +- tests/sim/tb/tb_sdffce.v | 2 +- tests/sim/tb/tb_sdffe.v | 2 +- tests/svtypes/struct_simple.sv | 2 +- tests/techmap/dfflibmap_dffn_dffe.lib | 4 +- tests/various/bug1531.ys | 2 +- tests/various/bug1745.ys | 2 +- tests/various/bug4865.ys | 2 +- tests/various/check_4.ys | 2 +- tests/various/dynamic_part_select.ys | 4 +- tests/various/dynamic_part_select/latch_002.v | 2 +- .../dynamic_part_select/multiple_blocking.v | 2 +- .../various/dynamic_part_select/nonblocking.v | 4 +- .../various/dynamic_part_select/reset_test.v | 2 +- tests/various/dynamic_part_select/reversed.v | 2 +- tests/various/equiv_opt_undef.ys | 2 +- tests/various/fsm-arst.ys | 4 +- tests/various/muxpack.v | 4 +- tests/various/shregmap.v | 2 +- tests/various/stat.ys | 2 +- tests/various/stat_area_by_width.lib | 4 +- tests/various/stat_hierarchy.ys | 2 +- tests/verific/blackbox.ys | 2 +- tests/verific/blackbox_ql.ys | 4 +- tests/verific/bounds.vhd | 2 +- tests/verific/case.sv | 8 +- tests/verific/case.ys | 4 +- tests/verific/ext_ramnet_err.sv | 2 +- tests/verific/range_case.ys | 4 +- tests/verific/rom_case.ys | 4 +- tests/verilog/param_default.ys | 2 +- tests/verilog/string-literals.ys | 2 +- 317 files changed, 3136 insertions(+), 3136 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 543209a83..2fd576a90 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -11,7 +11,7 @@ Yosys 0.65 .. Yosys 0.66 - C++ compiler with C++20 support is required. - Please be aware that next release will also migrate to CMake build system. - + * New commands and options - Added "lattice_dsp_nexus" pass for Lattice Nexus DSP inference. @@ -78,7 +78,7 @@ Yosys 0.61 .. Yosys 0.62 cascaded cells into tree of cells to improve timing. - Added "-gatesi" option to "write_blif" pass to init gates under gates_mode in BLIF format. - - Added "-on" and "-off" options to "debug" pass for + - Added "-on" and "-off" options to "debug" pass for persistent debug logging. - Added "linux_perf" pass to control performance recording. @@ -92,7 +92,7 @@ Yosys 0.60 .. Yosys 0.61 * New commands and options - Added "design_equal" pass to support fuzz-test comparison. - Added "lut2bmux" pass to convert $lut to $bmux. - - Added "-legalize" option to "read_rtlil" pass to prevent + - Added "-legalize" option to "read_rtlil" pass to prevent semantic errors. Yosys 0.59 .. Yosys 0.60 @@ -196,7 +196,7 @@ Yosys 0.53 .. Yosys 0.54 - Enable single-bit vector wires in RTLIL. * Xilinx support - - Single-port URAM mapping to support memories 2048 x 144b + - Single-port URAM mapping to support memories 2048 x 144b Yosys 0.52 .. Yosys 0.53 -------------------------- @@ -222,7 +222,7 @@ Yosys 0.51 .. Yosys 0.52 -------------------------- * New commands and options - Added "-pattern-limit" option to "share" pass to limit analysis effort. - - Added "libcache" pass to control caching of technology library + - Added "libcache" pass to control caching of technology library data parsed from liberty files. - Added "read_verilog_file_list" to parse verilog file list. @@ -288,7 +288,7 @@ Yosys 0.47 .. Yosys 0.48 * Gowin support - Added "-family" option to "synth_gowin" pass. - - Cell definitions split by family. + - Cell definitions split by family. * Verific support - Improved blackbox support. @@ -315,7 +315,7 @@ Yosys 0.45 .. Yosys 0.46 - Added new "functional backend" infrastructure with three example backends (C++, SMTLIB and Rosette). - Added new coarse-grain buffer cell type "$buf" to RTLIL. - - Added "-y" command line option to execute a Python script with + - Added "-y" command line option to execute a Python script with libyosys available as a built-in module. - Added support for casting to type in Verilog frontend. @@ -323,7 +323,7 @@ Yosys 0.45 .. Yosys 0.46 - Added "clockgate" pass for automatic clock gating cell insertion. - Added "bufnorm" experimental pass to convert design into buffered-normalized form. - - Added experimental "aiger2" and "xaiger2" backends, and an + - Added experimental "aiger2" and "xaiger2" backends, and an experimental "abc_new" command - Added "-force-detailed-loop-check" option to "check" pass. - Added "-unit_delay" option to "read_liberty" pass. @@ -348,10 +348,10 @@ Yosys 0.43 .. Yosys 0.44 - Build support for Haiku OS. * New commands and options - - Added "keep_hierarchy" pass to add attribute with + - Added "keep_hierarchy" pass to add attribute with same name to modules based on cost. - Added options "-noopt","-bloat" and "-check_cost" to - "test_cell" pass. + "test_cell" pass. * New back-ends - Added initial PolarFire support. ( synth_microchip ) @@ -365,22 +365,22 @@ Yosys 0.42 .. Yosys 0.43 * Verific support - Support building Yosys with various Verific library - configurations. Can be built now without YosysHQ + configurations. Can be built now without YosysHQ specific patch and extension library. Yosys 0.41 .. Yosys 0.42 -------------------------- * New commands and options - Added "box_derive" pass to derive box modules. - - Added option "assert-mod-count" to "select" pass. - - Added option "-header","-push" and "-pop" to "log" pass. + - Added option "assert-mod-count" to "select" pass. + - Added option "-header","-push" and "-pop" to "log" pass. * Intel support - Dropped Quartus support in "synth_intel_alm" pass. Yosys 0.40 .. Yosys 0.41 -------------------------- * New commands and options - - Added "cellmatch" pass for picking out standard cells automatically. + - Added "cellmatch" pass for picking out standard cells automatically. * Various - Extended the experimental incremental JSON API to allow arbitrary @@ -394,7 +394,7 @@ Yosys 0.40 .. Yosys 0.41 Yosys 0.39 .. Yosys 0.40 -------------------------- * New commands and options - - Added option "-vhdl2019" to "read" and "verific" pass. + - Added option "-vhdl2019" to "read" and "verific" pass. * Various - Major documentation overhaul. @@ -408,7 +408,7 @@ Yosys 0.39 .. Yosys 0.40 Yosys 0.38 .. Yosys 0.39 -------------------------- * New commands and options - - Added option "-extra-map" to "synth" pass. + - Added option "-extra-map" to "synth" pass. - Added option "-dont_use" to "dfflibmap" pass. - Added option "-href" to "show" command. - Added option "-noscopeinfo" to "flatten" pass. @@ -422,7 +422,7 @@ Yosys 0.38 .. Yosys 0.39 the hierarchy during flattening. - Added sequential area output to "stat -liberty". - Added ability to record/replay diagnostics in cxxrtl backend. - + * Verific support - Added attributes to module instantiation. @@ -469,7 +469,7 @@ Yosys 0.35 .. Yosys 0.36 * QuickLogic support - Added "K6N10f" support. - - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to + - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to "synth_quicklogic" pass. - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K. - Added "ql_bram_types" pass to change TDP36K depending on configuration. @@ -564,7 +564,7 @@ Yosys 0.29 .. Yosys 0.30 - Added remaining primitives blackboxes. * Various - - "show -colorattr" will now color the cells, wires, and + - "show -colorattr" will now color the cells, wires, and connection arrows. - "show -viewer none" will not execute viewer. @@ -739,7 +739,7 @@ Yosys 0.19 .. Yosys 0.20 operators were not affected. * Verific support - - Proper import of port ranges into Yosys, may result in reversed + - Proper import of port ranges into Yosys, may result in reversed bit-order of top-level ports for some synthesis flows. Yosys 0.18 .. Yosys 0.19 @@ -833,7 +833,7 @@ Yosys 0.14 .. Yosys 0.15 * SystemVerilog - Added support for accessing whole sub-structures in expressions - + * New commands and options - Added glift command, used to create gate-level information flow tracking (GLIFT) models by the "constructive mapping" approach @@ -848,7 +848,7 @@ Yosys 0.13 .. Yosys 0.14 - Added $bmux and $demux cells and related optimization patterns. * New commands and options - - Added "bmuxmap" and "dmuxmap" passes + - Added "bmuxmap" and "dmuxmap" passes - Added "-fst" option to "sim" pass for writing FST files - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate", "-sim-gold" options to "sim" pass for co-simulation diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cc1085f96..522929c50 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -95,7 +95,7 @@ struct XAigerWriter } bit2aig_stack.push_back(bit); - + // NB: Cannot use iterator returned from aig_map.insert() // since this function is called recursively diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 0451af4c7..128dbda6c 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -187,7 +187,7 @@ struct SmtModule { Functional::IR ir; SmtScope scope; std::string name; - + SmtStruct input_struct; SmtStruct output_struct; SmtStruct state_struct; @@ -256,7 +256,7 @@ struct SmtModule { } void write(std::ostream &out) - { + { SExprWriter w(out); input_struct.write_definition(w); @@ -266,7 +266,7 @@ struct SmtModule { w << list("declare-datatypes", list(list("Pair", 2)), list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y")))))); - + write_eval(w); write_initial(w); } diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index b37f948b6..1adceddd5 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -304,7 +304,7 @@ struct SmtrModule { } void write(std::ostream &out) - { + { SExprWriter w(out); input_struct.write_definition(w); diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 343fcfc0f..d6a1ce4af 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -46,7 +46,7 @@ struct MemContentsTest { error: printf("FAIL\n"); int digits = (data_width + 3) / 4; - + for(auto addr = 0; addr < (1< 1: return len(self.bits[1]) else: return sum([sig.width for sig in self.signals if not sig.init_only]) - + def first_step(self): values = WitnessValues() # may have issues when non_init_bits is 0 diff --git a/cmake/YosysAbc.cmake b/cmake/YosysAbc.cmake index 6e3736712..0632a9b17 100644 --- a/cmake/YosysAbc.cmake +++ b/cmake/YosysAbc.cmake @@ -57,7 +57,7 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) target_include_directories(${arg_LIBNAME} PRIVATE abc/src) target_compile_definitions(${arg_LIBNAME} PUBLIC WIN32_NO_DLL - $<$>:ABC_NAMESPACE=abc> + $<$>:ABC_NAMESPACE=abc> ABC_USE_STDINT_H=1 ABC_USE_CUDD=1 ABC_NO_DYNAMIC_LINKING @@ -68,11 +68,11 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) $<$:HAVE_STRUCT_TIMESPEC> ABC_NO_RLIMIT ) - target_compile_options(${arg_LIBNAME} PRIVATE + target_compile_options(${arg_LIBNAME} PRIVATE $<$:/wd4576> $<$:/Zc:strictStrings-> ) - + target_safe_compile_options(${arg_LIBNAME} PRIVATE -fpermissive -fno-exceptions diff --git a/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst b/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst index ff404cb53..181bdaa0a 100644 --- a/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst +++ b/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst @@ -279,9 +279,9 @@ This document was originally published in April 2015: in line 13 provides a mini synthesis-script to be used to process this cell. .. code-block:: c - :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled - using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a - -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` + :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled + using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a + -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` set and booted with a custom setup routine written in ARM assembler. :name: sieve diff --git a/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst b/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst index 1874b0148..58a0ac39b 100644 --- a/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst +++ b/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst @@ -18,7 +18,7 @@ be used to convert Verilog designs with simple assertions to BTOR format. Download ======== -This document was originally published in November 2013: +This document was originally published in November 2013: :download:`Converting Verilog to BTOR PDF` .. diff --git a/docs/source/appendix/primer.rst b/docs/source/appendix/primer.rst index f54f99e52..beb1e6a8a 100644 --- a/docs/source/appendix/primer.rst +++ b/docs/source/appendix/primer.rst @@ -601,7 +601,7 @@ Let's consider the following BNF (in Bison syntax): :class: width-helper invert-helper :name: fig:Basics_parsetree - Example parse tree for the Verilog expression + Example parse tree for the Verilog expression :verilog:`assign foo = bar + 42;` The parser converts the token list to the parse tree in :numref:`Fig. %s @@ -630,7 +630,7 @@ three-address-code intermediate representation. :cite:p:`Dragonbook` :class: width-helper invert-helper :name: fig:Basics_ast - Example abstract syntax tree for the Verilog expression + Example abstract syntax tree for the Verilog expression :verilog:`assign foo = bar + 42;` diff --git a/docs/source/appendix/rtlil_text.rst b/docs/source/appendix/rtlil_text.rst index 352b1af2e..f555d565e 100644 --- a/docs/source/appendix/rtlil_text.rst +++ b/docs/source/appendix/rtlil_text.rst @@ -136,11 +136,11 @@ wires, memories, cells, processes, and connections. ::= * ::= module - ::= ( + ::= ( | - | - | - | + | + | + | | )* ::= parameter ? ::= | | @@ -170,9 +170,9 @@ See :ref:`sec:rtlil_sigspec` for an overview of signal specifications. .. code:: BNF - ::= + ::= | - | [ (:)? ] + | [ (:)? ] | { * } When a ```` is specified, the wire must have been previously declared. @@ -202,12 +202,12 @@ See :ref:`sec:rtlil_cell_wire` for an overview of wires. ::= * ::= wire * ::= - ::= width - | offset - | input - | output - | inout - | upto + ::= width + | offset + | input + | output + | inout + | upto | signed Memories @@ -223,8 +223,8 @@ See :ref:`sec:rtlil_memory` for an overview of memory cells, and ::= * ::= memory * - ::= width - | size + ::= width + | size | offset Cells @@ -299,9 +299,9 @@ be: .. code:: BNF ::= * - ::= sync + ::= sync | sync global - | sync init + | sync init | sync always ::= low | high | posedge | negedge | edge ::= update diff --git a/docs/source/cell/word_logic.rst b/docs/source/cell/word_logic.rst index 9f04e9b99..fadbec140 100644 --- a/docs/source/cell/word_logic.rst +++ b/docs/source/cell/word_logic.rst @@ -29,7 +29,7 @@ There are 2 products to be summed, so ``\DEPTH`` shall be 2. ~A[1]---+|| A[1]--+||| ~A[0]-+|||| - A[0]+||||| + A[0]+||||| |||||| product formula 010000 ~\A[0] 001001 \A[1]~\A[2] diff --git a/docs/source/cmd/index_internal.rst b/docs/source/cmd/index_internal.rst index ab9c13aba..afd194c73 100644 --- a/docs/source/cmd/index_internal.rst +++ b/docs/source/cmd/index_internal.rst @@ -88,7 +88,7 @@ Dumping command help to json by ``Pass::experimental()``) * also title (``short_help`` argument in ``Pass::Pass``), group, and class name - + + dictionary of group name to list of commands in that group - used by sphinx autodoc to generate help content @@ -106,7 +106,7 @@ Dumping command help to json code block is formatted as ``yoscrypt`` (e.g. `synth_ice40`). The caveat here is that if the ``script()`` calls ``run()`` on any commands *prior* to the first ``check_label`` then the auto detection will break and revert to - unformatted code (e.g. `synth_fabulous`). + unformatted code (e.g. `synth_fabulous`). Command line rendering ~~~~~~~~~~~~~~~~~~~~~~ @@ -114,7 +114,7 @@ Command line rendering - if ``Pass::formatted_help()`` returns true, will call ``PrettyHelp::log_help()`` - + traverse over the children of the root node and render as plain text + + traverse over the children of the root node and render as plain text + effectively the reverse of converting unformatted ``Pass::help()`` text + lines are broken at 80 characters while maintaining indentation (controlled by ``MAX_LINE_LEN`` in :file:`kernel/log_help.cc`) diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile index eab8349da..623ca9968 100644 --- a/docs/source/code_examples/fifo/Makefile +++ b/docs/source/code_examples/fifo/Makefile @@ -2,7 +2,7 @@ include ../../../common.mk DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse -MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates +MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells DOTS := $(addsuffix .dot,$(DOT_NAMES)) diff --git a/docs/source/code_examples/fifo/fifo.v b/docs/source/code_examples/fifo/fifo.v index 86f292406..db99f7211 100644 --- a/docs/source/code_examples/fifo/fifo.v +++ b/docs/source/code_examples/fifo/fifo.v @@ -1,5 +1,5 @@ // address generator/counter -module addr_gen +module addr_gen #( parameter MAX_DATA=256, localparam AWIDTH = $clog2(MAX_DATA) ) ( input en, clk, rst, @@ -21,7 +21,7 @@ module addr_gen endmodule //addr_gen // Define our top level fifo entity -module fifo +module fifo #( parameter MAX_DATA=256, localparam AWIDTH = $clog2(MAX_DATA) ) ( input wen, ren, clk, rst, diff --git a/docs/source/code_examples/fifo/fifo.ys b/docs/source/code_examples/fifo/fifo.ys index e6b9bf69d..d8af9a7fd 100644 --- a/docs/source/code_examples/fifo/fifo.ys +++ b/docs/source/code_examples/fifo/fifo.ys @@ -2,7 +2,7 @@ # throw in some extra text to match what we expect if we were opening an # interactive terminal log $ yosys fifo.v -log +log log -- Parsing `fifo.v' using frontend ` -vlog2k' -- read_verilog -defer fifo.v diff --git a/docs/source/code_examples/macro_commands/synth_ice40.ys b/docs/source/code_examples/macro_commands/synth_ice40.ys index e9b36bb35..fbdd763fc 100644 --- a/docs/source/code_examples/macro_commands/synth_ice40.ys +++ b/docs/source/code_examples/macro_commands/synth_ice40.ys @@ -54,7 +54,7 @@ map_gates: ice40_wrapcarry techmap opt -fast - abc -dff -D 1 + abc -dff -D 1 ice40_opt map_ffs: @@ -88,4 +88,4 @@ check: stat check -noinit blackbox =A:whitebox - + diff --git a/docs/source/code_examples/opt/opt_expr.ys b/docs/source/code_examples/opt/opt_expr.ys index e87da339e..f884b2227 100644 --- a/docs/source/code_examples/opt/opt_expr.ys +++ b/docs/source/code_examples/opt/opt_expr.ys @@ -3,7 +3,7 @@ read_verilog <`. .. todo:: consider a brief glossary for terms like adff .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/proc` - :doc:`/using_yosys/synthesis/opt` @@ -321,7 +321,7 @@ and merged with the ``raddr`` wire feeding into the `$memrd` cell. This wire merging happened during the call to `clean` which we can see in the :ref:`flat_clean`. -.. note:: +.. note:: `flatten` and `clean` would normally be combined into a single :yoterm:`yosys> flatten;;` output, but they appear separately here as @@ -394,7 +394,7 @@ highlighted below: ``rdata`` output after `opt_dff` .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/fsm` - :doc:`/using_yosys/synthesis/opt` @@ -461,7 +461,7 @@ memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and ``SRST=1'0``) inputs. .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/opt` - :doc:`/using_yosys/synthesis/techmap_synth` - :doc:`/using_yosys/synthesis/memory` @@ -659,7 +659,7 @@ into flip flops (the ``logic fallback``) with `memory_map`. complex. .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/techmap_synth` - :doc:`/using_yosys/synthesis/memory` @@ -757,7 +757,7 @@ cells. ``rdata`` output after :ref:`map_cells` .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/techmap_synth` - :doc:`/using_yosys/synthesis/abc` diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst index cbbe5aa31..ff6f3ac49 100644 --- a/docs/source/getting_started/installation.rst +++ b/docs/source/getting_started/installation.rst @@ -152,7 +152,7 @@ Installing all prerequisites: recommended to use Windows Subsystem for Linux (WSL) and follow the instructions for Ubuntu. -.. +.. tab:: MSYS2 (MINGW64) .. code:: console diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst index c44ce82a8..d6e482431 100644 --- a/docs/source/getting_started/scripting_intro.rst +++ b/docs/source/getting_started/scripting_intro.rst @@ -149,11 +149,11 @@ represent, see :ref:`interactive_show` and the Calling :yoscrypt:`show addr_gen` after `hierarchy` -.. note:: +.. note:: The `show` command requires a working installation of `GraphViz`_ and `xdot`_ for displaying the actual circuit diagrams. - + .. _GraphViz: http://www.graphviz.org/ .. _xdot: https://github.com/jrfonseca/xdot.py diff --git a/docs/source/introduction.rst b/docs/source/introduction.rst index 376c8043b..48a4fb9fd 100644 --- a/docs/source/introduction.rst +++ b/docs/source/introduction.rst @@ -125,7 +125,7 @@ The first version of the Yosys documentation was published as a bachelor thesis at the Vienna University of Technology :cite:p:`BACC`. :Abstract: - Most of today's digital design is done in HDL code (mostly Verilog or + Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or @@ -164,14 +164,14 @@ for specialised tasks. Benefits of open source HDL synthesis ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Cost (also applies to ``free as in free beer`` solutions): - +- Cost (also applies to ``free as in free beer`` solutions): + Today the cost for a mask set in 180nm technology is far less than the cost for the design tools needed to design the mask layouts. Open Source ASIC flows are an important enabler for ASIC-level Open Source Hardware. -- Availability and Reproducibility: - +- Availability and Reproducibility: + If you are a researcher who is publishing, you want to use tools that everyone else can also use. Even if most universities have access to all major commercial tools, you usually do not have easy access to the version that was @@ -179,14 +179,14 @@ Benefits of open source HDL synthesis can even release the source code of the tool you have used alongside your data. -- Framework: - +- Framework: + Yosys is not only a tool. It is a framework that can be used as basis for other developments, so researchers and hackers alike do not need to re-invent the basic functionality. Extensibility was one of Yosys' design goals. -- All-in-one: - +- All-in-one: + Because of the framework characteristics of Yosys, an increasing number of features become available in one tool. Yosys not only can be used for circuit synthesis but also for formal equivalence checking, SAT solving, and for @@ -194,8 +194,8 @@ Benefits of open source HDL synthesis proprietary software one needs to learn a new tool for each of these applications. -- Educational Tool: - +- Educational Tool: + Proprietary synthesis tools are at times very secretive about their inner workings. They often are ``black boxes``. Yosys is very open about its internals and it is easy to observe the different steps of synthesis. diff --git a/docs/source/literature.bib b/docs/source/literature.bib index 143e3aa36..6d35d2922 100644 --- a/docs/source/literature.bib +++ b/docs/source/literature.bib @@ -66,24 +66,24 @@ year = {1996} } -@ARTICLE{Verilog2005, +@ARTICLE{Verilog2005, journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)}, - title={IEEE Standard for Verilog Hardware Description Language}, + title={IEEE Standard for Verilog Hardware Description Language}, author={IEEE Standards Association and others}, - year={2006}, + year={2006}, doi={10.1109/IEEESTD.2006.99495} } -@ARTICLE{VerilogSynth, +@ARTICLE{VerilogSynth, journal={IEEE Std 1364.1-2002}, - title={IEEE Standard for Verilog Register Transfer Level Synthesis}, + title={IEEE Standard for Verilog Register Transfer Level Synthesis}, author={IEEE Standards Association and others}, - year={2002}, + year={2002}, doi={10.1109/IEEESTD.2002.94220} } @ARTICLE{VHDL, - journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, + journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual}, author={IEEE Standards Association and others}, year={2009}, @@ -92,20 +92,20 @@ } @ARTICLE{VHDLSynth, - journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, + journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis}, author={IEEE Standards Association and others}, year={2004}, doi={10.1109/IEEESTD.2004.94802} } -@ARTICLE{IP-XACT, - journal={IEEE Std 1685-2009}, - title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, +@ARTICLE{IP-XACT, + journal={IEEE Std 1685-2009}, + title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, author={IEEE Standards Association and others}, - year={2010}, - pages={C1-360}, - keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, + year={2010}, + pages={C1-360}, + keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, doi={10.1109/IEEESTD.2010.5417309} } @@ -116,7 +116,7 @@ isbn = {0-201-10088-6}, publisher = {Addison-Wesley Longman Publishing Co., Inc.}, address = {Boston, MA, USA} -} +} @INPROCEEDINGS{Cummings00, author = {Clifford E. Cummings and Sunburst Design Inc}, @@ -132,26 +132,26 @@ year={August 1967} } -@INPROCEEDINGS{fsmextract, - author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, - booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, - title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, - year={2010}, - pages={2610-2613}, - keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, +@INPROCEEDINGS{fsmextract, + author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, + booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, + title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, + year={2010}, + pages={2610-2613}, + keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, doi={10.1109/ISCAS.2010.5537093}, } -@ARTICLE{MultiLevelLogicSynth, - author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, - journal={Proceedings of the IEEE}, - title={Multilevel logic synthesis}, - year={1990}, - volume={78}, - number={2}, - pages={264-300}, - keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, - doi={10.1109/5.52213}, +@ARTICLE{MultiLevelLogicSynth, + author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, + journal={Proceedings of the IEEE}, + title={Multilevel logic synthesis}, + year={1990}, + volume={78}, + number={2}, + pages={264-300}, + keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, + doi={10.1109/5.52213}, ISSN={0018-9219}, } @@ -171,7 +171,7 @@ acmid = {321925}, publisher = {ACM}, address = {New York, NY, USA}, -} +} @article{een2003temporal, title={Temporal induction by incremental SAT solving}, diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index 0d1a17503..ae349bb21 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -56,7 +56,7 @@ is shown. .. figure:: /_images/code_examples/show/example_first.* :class: width-helper invert-helper - + Output of the first `show` command in :numref:`example_ys` The first output shows the design directly after being read by the Verilog @@ -88,7 +88,7 @@ multiplexer and a d-type flip-flop, which brings us to the second diagram: .. figure:: /_images/code_examples/show/example_second.* :class: width-helper invert-helper - + Output of the second `show` command in :numref:`example_ys` The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if @@ -106,14 +106,14 @@ operations, it is therefore recommended to always call `clean` before calling `show`. In this script we directly call `opt` as the next step, which finally leads us -to the third diagram: +to the third diagram: .. figure:: /_images/code_examples/show/example_third.* :class: width-helper invert-helper :name: example_out - + Output of the third `show` command in :ref:`example_ys` - + Here we see that the `opt` command not only has removed the artifacts left behind by `proc`, but also determined correctly that it can remove the first `$mux` cell without changing the behavior of the circuit. @@ -167,7 +167,7 @@ mapped to a cell library: :class: width-helper invert-helper :name: first_pitfall - A half-adder built from simple CMOS gates, demonstrating common pitfalls when + A half-adder built from simple CMOS gates, demonstrating common pitfalls when using `show` .. literalinclude:: /code_examples/show/cmos.ys @@ -176,7 +176,7 @@ mapped to a cell library: :end-at: cmos_00 :name: pitfall_code :caption: Generating :numref:`first_pitfall` - + First, Yosys did not have access to the cell library when this diagram was generated, resulting in all cell ports defaulting to being inputs. This is why all ports are drawn on the left side the cells are awkwardly arranged in a large @@ -248,7 +248,7 @@ command already fails to verify, it is better to troubleshoot the coarse-grain version of the circuit before `techmap` than the gate-level circuit after `techmap`. -.. Note:: +.. Note:: It is generally recommended to verify the internal state of a design by writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and @@ -327,7 +327,7 @@ tools). - :cmd:title:`dump`. - :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize a design dynamically. - + The code used is included in the Yosys code base under |code_examples/scrambler|_. @@ -438,7 +438,7 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`: .. figure:: /_images/code_examples/selections/memdemo_00.* :class: width-helper invert-helper - + ``memdemo`` Because this produces a rather large circuit, it can be useful to split it into @@ -459,18 +459,18 @@ below. .. figure:: /_images/code_examples/selections/submod_02.* :class: width-helper invert-helper - + ``outstage`` .. figure:: /_images/code_examples/selections/submod_03.* :class: width-helper invert-helper :name: selstage - + ``selstage`` .. figure:: /_images/code_examples/selections/submod_01.* :class: width-helper invert-helper - + ``scramble`` Evaluation of combinatorial circuits @@ -541,9 +541,9 @@ to solve this kind of problems. .. _MiniSAT: http://minisat.se/ -.. note:: - - While it is possible to perform model checking directly in Yosys, it +.. note:: + + While it is possible to perform model checking directly in Yosys, it is highly recommended to use SBY or EQY for formal hardware verification. The `sat` command works very similar to the `eval` command. The main difference diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst index 9aa028418..178df5682 100644 --- a/docs/source/using_yosys/more_scripting/load_design.rst +++ b/docs/source/using_yosys/more_scripting/load_design.rst @@ -81,7 +81,7 @@ Yosys frontends 'Frontend' here means that the command is implemented as a sub-class of ``RTLIL::Frontend``, as opposed to the usual ``RTLIL::Pass``. -.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under +.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under :doc:`/yosys_internals/extending_yosys/index` The `read_verilog` command diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst index 1f3912956..bfabb7a01 100644 --- a/docs/source/using_yosys/more_scripting/selections.rst +++ b/docs/source/using_yosys/more_scripting/selections.rst @@ -35,8 +35,8 @@ selection; while :yoscrypt:`delete foobar` will only delete the module foobar. If no `select` command has been made, then the "current selection" will be the whole design. -.. note:: Many of the examples on this page make use of the `show` - command to visually demonstrate the effect of selections. For a more +.. note:: Many of the examples on this page make use of the `show` + command to visually demonstrate the effect of selections. For a more detailed look at this command, refer to :ref:`interactive_show`. How to make a selection @@ -106,7 +106,7 @@ glance. When it is called with multiple arguments, each argument is evaluated and pushed separately on a stack. After all arguments have been processed it simply creates the union of all elements on the stack. So :yoscrypt:`select t:$add a:foo` will select all `$add` cells and all objects with the ``foo`` -attribute set: +attribute set: .. literalinclude:: /code_examples/selections/foobaraddsub.v :caption: Test module for operations on selections @@ -130,7 +130,7 @@ select all `$add` cells that have the ``foo`` attribute set: .. code-block:: :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub` - + yosys> select t:$add a:foo %i -list foobaraddsub/$add$foobaraddsub.v:4$1 @@ -282,7 +282,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the .. figure:: /_images/code_examples/selections/memdemo_00.* :class: width-helper invert-helper :name: memdemo_00 - + Complete circuit diagram for the design shown in :numref:`memdemo_src` There's a lot going on there, but maybe we are only interested in the tree of @@ -293,7 +293,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`: .. figure:: /_images/code_examples/selections/memdemo_01.* :class: width-helper invert-helper :name: memdemo_01 - + Output of :yoscrypt:`show y %ci2` From this we would learn that ``y`` is driven by a `$dff` cell, that ``y`` is @@ -305,7 +305,7 @@ start of the name). Let's go a bit further now and try :yoscrypt:`show y %ci5`: .. figure:: /_images/code_examples/selections/memdemo_02.* :class: width-helper invert-helper :name: memdemo_02 - + Output of :yoscrypt:`show y %ci5` That's starting to get a bit messy, so maybe we want to ignore the mux select @@ -319,7 +319,7 @@ type with :yoscrypt:`show y %ci5:-$mux[S]`: .. figure:: /_images/code_examples/selections/memdemo_03.* :class: width-helper invert-helper :name: memdemo_03 - + Output of :yoscrypt:`show y %ci5:-$mux[S]` We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D] @@ -330,7 +330,7 @@ multiplexer select inputs and flip-flop cells: .. figure:: /_images/code_examples/selections/memdemo_05.* :class: width-helper invert-helper :name: memdemo_05 - + Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff`` Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following @@ -342,7 +342,7 @@ ignoring any ports named ``CLK`` or ``S``: .. figure:: /_images/code_examples/selections/memdemo_04.* :class: width-helper invert-helper :name: memdemo_04 - + Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux` Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst index 50811fd1e..073a05213 100644 --- a/docs/source/using_yosys/synthesis/cell_libs.rst +++ b/docs/source/using_yosys/synthesis/cell_libs.rst @@ -18,7 +18,7 @@ detail in the :doc:`/getting_started/example_synth` document. The :file:`counter.ys` script includes the commands used to generate the images in this document. Code snippets in this document skip these commands; including line numbers to allow the reader to follow along with the source. - + To learn more about these commands, check out :ref:`interactive_show`. .. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro @@ -37,7 +37,7 @@ First, let's quickly look at the design: This is a simple counter with reset and enable. If the reset signal, ``rst``, is high then the counter will reset to 0. Otherwise, if the enable signal, ``en``, is high then the ``count`` register will increment by 1 each rising edge -of the clock, ``clk``. +of the clock, ``clk``. Loading the design ~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/using_yosys/synthesis/extract.rst b/docs/source/using_yosys/synthesis/extract.rst index 8c346412a..c59ac5363 100644 --- a/docs/source/using_yosys/synthesis/extract.rst +++ b/docs/source/using_yosys/synthesis/extract.rst @@ -24,7 +24,7 @@ Example code can be found in |code_examples/macc|_. .. figure:: /_images/code_examples/macc/macc_simple_test_00a.* :class: width-helper invert-helper - + before `extract` .. literalinclude:: /code_examples/macc/macc_simple_test.ys @@ -33,7 +33,7 @@ Example code can be found in |code_examples/macc|_. .. figure:: /_images/code_examples/macc/macc_simple_test_00b.* :class: width-helper invert-helper - + after `extract` .. literalinclude:: /code_examples/macc/macc_simple_test.v diff --git a/docs/source/using_yosys/synthesis/fsm.rst b/docs/source/using_yosys/synthesis/fsm.rst index 07a3cc9cc..2da0b1896 100644 --- a/docs/source/using_yosys/synthesis/fsm.rst +++ b/docs/source/using_yosys/synthesis/fsm.rst @@ -92,7 +92,7 @@ transition table. For each state: 3. Set the state signal to the current state 4. Try to evaluate the next state and control output 5. If step 4 was not successful: - + - Recursively goto step 4 with the offending stop-signal set to 0. - Recursively goto step 4 with the offending stop-signal set to 1. diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst index b498bcb1d..44d5698b5 100644 --- a/docs/source/using_yosys/synthesis/memory.rst +++ b/docs/source/using_yosys/synthesis/memory.rst @@ -122,7 +122,7 @@ to four memory primitive classes available for selection: - Can handle arbitrary number and kind of read ports - LUT RAM (aka distributed RAM): uses LUT storage as RAM - + - Supported on most FPGAs (with notable exception of ice40) - Usually has one synchronous write port, one or more asynchronous read ports - Small @@ -141,7 +141,7 @@ to four memory primitive classes available for selection: - Huge RAM: - Only supported on several targets: - + - Some Xilinx UltraScale devices (UltraRAM) - Two ports, both with mutually exclusive synchronous read and write @@ -154,7 +154,7 @@ to four memory primitive classes available for selection: - Does not support initial data - Nexus (large RAM) - + - Two ports, both with mutually exclusive synchronous read and write - Single clock @@ -304,7 +304,7 @@ Synchronous SDP with undefined collision behavior if (read_enable) begin read_data <= mem[read_addr]; - + if (write_enable && read_addr == write_addr) // this if block read_data <= 'x; @@ -322,7 +322,7 @@ Synchronous SDP with undefined collision behavior if (write_enable) mem[write_addr] <= write_data; - if (read_enable) + if (read_enable) read_data <= mem[read_addr]; end @@ -446,7 +446,7 @@ Synchronous single-port RAM with write-first behavior if (read_enable) if (write_enable) read_data <= write_data; - else + else read_data <= mem[addr]; end diff --git a/docs/source/using_yosys/synthesis/techmap_synth.rst b/docs/source/using_yosys/synthesis/techmap_synth.rst index 54a715342..c22269fdf 100644 --- a/docs/source/using_yosys/synthesis/techmap_synth.rst +++ b/docs/source/using_yosys/synthesis/techmap_synth.rst @@ -1,4 +1,4 @@ -Technology mapping +Technology mapping ================== .. todo:: less academic, check text is coherent diff --git a/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst b/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst index 22e4b1b7a..64dd36d0e 100644 --- a/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst +++ b/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst @@ -240,7 +240,7 @@ the design at each log header. A worked example ~~~~~~~~~~~~~~~~ - + Say you did all the minimization and found that an error in `synth_xilinx` occurs when a call to ``techmap -map +/xilinx/cells_map.v`` with ``MIN_MUX_INPUTS`` defined parses a `$_MUX16_` with all inputs set to ``1'x``. diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst index 949c78586..315ae9c58 100644 --- a/docs/source/yosys_internals/extending_yosys/extensions.rst +++ b/docs/source/yosys_internals/extending_yosys/extensions.rst @@ -68,7 +68,7 @@ with, and lists off the current design's modules. :language: c++ :lines: 1, 4, 6, 7-20 :caption: Example command :yoscrypt:`my_cmd` from :file:`my_cmd.cc` - + Note that we are making a global instance of a class derived from ``Yosys::Pass``, which we get by including :file:`kernel/yosys.h`. diff --git a/docs/source/yosys_internals/flow/index.rst b/docs/source/yosys_internals/flow/index.rst index e5afa2540..565cea2bb 100644 --- a/docs/source/yosys_internals/flow/index.rst +++ b/docs/source/yosys_internals/flow/index.rst @@ -10,7 +10,7 @@ These scripts contain three types of commands: - **Backends**, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .). -.. toctree:: +.. toctree:: :maxdepth: 3 overview diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index 8381641b3..73a67f2f2 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -432,12 +432,12 @@ variables: initialization of ``AST_INTERNAL::ProcessGenerator`` these two variables are empty. -- | ``subst_lvalue_from`` and ``subst_lvalue_to`` +- | ``subst_lvalue_from`` and ``subst_lvalue_to`` | These two variables contain the mapping from left-hand-side signals (``\ ``) to the current temporary signal for the same thing (initially ``$0\ ``). -- | ``current_case`` +- | ``current_case`` | A pointer to a ``RTLIL::CaseRule`` object. Initially this is the root case of the generated ``RTLIL::Process``. @@ -603,13 +603,13 @@ behavioural model in ``RTLIL::Process`` representation. The actual conversion from a behavioural model to an RTL representation is performed by the `proc` pass and the passes it launches: -- | `proc_clean` and `proc_rmdead` +- | `proc_clean` and `proc_rmdead` | These two passes just clean up the ``RTLIL::Process`` structure. The `proc_clean` pass removes empty parts (eg. empty assignments) from the process and `proc_rmdead` detects and removes unreachable branches from the process's decision trees. -- | `proc_arst` +- | `proc_arst` | This pass detects processes that describe d-type flip-flops with asynchronous resets and rewrites the process to better reflect what they are modelling: Before this pass, an asynchronous reset has two @@ -617,7 +617,7 @@ pass and the passes it launches: reset path. After this pass the sync rule for the reset is level-sensitive and the top-level ``RTLIL::SwitchRule`` has been removed. -- | `proc_mux` +- | `proc_mux` | This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to a tree of multiplexers per written signal. After this, the ``RTLIL::Process`` structure only contains the ``RTLIL::SyncRule`` s that diff --git a/docs/source/yosys_internals/formats/index.rst b/docs/source/yosys_internals/formats/index.rst index 22d9e964a..a6c29955e 100644 --- a/docs/source/yosys_internals/formats/index.rst +++ b/docs/source/yosys_internals/formats/index.rst @@ -48,7 +48,7 @@ RTLIL and fail to run when unsupported high-level constructs are used. In such cases a pass that transforms the higher-level constructs to lower-level constructs must be called from the synthesis script first. -.. toctree:: +.. toctree:: :maxdepth: 3 rtlil_rep diff --git a/docs/tests/macro_commands.py b/docs/tests/macro_commands.py index acd02e674..cded283b3 100755 --- a/docs/tests/macro_commands.py +++ b/docs/tests/macro_commands.py @@ -94,7 +94,7 @@ for macro in MACRO_SOURCE.glob("*.ys"): if expected_dict[key] and expected_dict[key] != actual_dict[key]: does_match = False - # raise error on mismatch + # raise error on mismatch if not does_match: logging.error(f"Expected {expected!r}, got {actual!r}") raise_error = True diff --git a/docs/util/RtlilLexer.py b/docs/util/RtlilLexer.py index 75aa53ec8..93a401515 100644 --- a/docs/util/RtlilLexer.py +++ b/docs/util/RtlilLexer.py @@ -9,7 +9,7 @@ class RtlilLexer(RegexLexer): filenames = ['*.il'] keyword_re = r'(always|assign|attribute|autoidx|case|cell|connect|edge|end|global|high|init|inout|input|low|memory|module|negedge|offset|output|parameter|posedge|process|real|signed|size|switch|sync|update|upto|width|wire)' - + tokens = { 'common': [ (r'\s+', Whitespace), diff --git a/docs/util/cell_documenter.py b/docs/util/cell_documenter.py index 58e65c2ea..296ae1bfd 100644 --- a/docs/util/cell_documenter.py +++ b/docs/util/cell_documenter.py @@ -34,7 +34,7 @@ class YosysCell: inputs: list[str] outputs: list[str] properties: list[str] - + class YosysCellGroupDocumenter(Documenter): objtype = 'cellgroup' priority = 10 @@ -67,7 +67,7 @@ class YosysCellGroupDocumenter(Documenter): for (name, obj) in cells_obj.get(self.lib_key, {}).items(): self.__cell_lib[name] = obj return self.__cell_lib - + @classmethod def can_document_member( cls, @@ -83,7 +83,7 @@ class YosysCellGroupDocumenter(Documenter): self.content_indent = '' self.fullname = self.modname = self.name return True - + def import_object(self, raiseerror: bool = False) -> bool: # get cell try: @@ -95,16 +95,16 @@ class YosysCellGroupDocumenter(Documenter): self.real_modname = self.modname return True - + def get_sourcename(self) -> str: return self.env.doc2path(self.env.docname) - + def format_name(self) -> str: return self.options.caption or '' def format_signature(self, **kwargs: Any) -> str: return self.modname - + def add_directive_header(self, sig: str) -> None: domain = getattr(self, 'domain', 'cell') directive = getattr(self, 'directivetype', 'group') @@ -118,7 +118,7 @@ class YosysCellGroupDocumenter(Documenter): if self.options.noindex: self.add_line(' :noindex:', sourcename) - + def add_content(self, more_content: Any | None) -> None: # groups have no native content # add additional content (e.g. from document), if present @@ -271,22 +271,22 @@ class YosysCellDocumenter(YosysCellGroupDocumenter): self.fullname = ((self.modname) + (thing or '')) return True - + def import_object(self, raiseerror: bool = False) -> bool: if super().import_object(raiseerror): self.object = YosysCell(self.modname, **self.object[1]) return True return False - + def get_sourcename(self) -> str: return self.object.source.split(":")[0] - + def format_name(self) -> str: return self.object.name def format_signature(self, **kwargs: Any) -> str: return self.groupname + self.fullname + self.attribute - + def add_directive_header(self, sig: str) -> None: domain = getattr(self, 'domain', self.objtype) directive = getattr(self, 'directivetype', 'def') @@ -310,7 +310,7 @@ class YosysCellDocumenter(YosysCellGroupDocumenter): if self.options.noindex: self.add_line(' :noindex:', sourcename) - + def add_content(self, more_content: Any | None) -> None: # set sourcename and add content from attribute documentation sourcename = self.get_sourcename() @@ -360,7 +360,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter): if isinstance(parent, YosysCellDocumenter): return True return False - + def add_directive_header(self, sig: str) -> None: domain = getattr(self, 'domain', 'cell') directive = getattr(self, 'directivetype', 'source') @@ -383,7 +383,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter): if self.options.noindex: self.add_line(' :noindex:', sourcename) - + def add_content(self, more_content: Any | None) -> None: # set sourcename and add content from attribute documentation sourcename = self.get_sourcename() diff --git a/docs/util/cmd_documenter.py b/docs/util/cmd_documenter.py index 9347d8ffd..2c9384cca 100644 --- a/docs/util/cmd_documenter.py +++ b/docs/util/cmd_documenter.py @@ -78,7 +78,7 @@ class YosysCmd: self.source_func = source_func self.experimental_flag = experimental_flag self.internal_flag = internal_flag - + class YosysCmdGroupDocumenter(Documenter): objtype = 'cmdgroup' priority = 10 @@ -112,7 +112,7 @@ class YosysCmdGroupDocumenter(Documenter): for (name, obj) in cmds_obj.get(self.lib_key, {}).items(): self.__cmd_lib[name] = obj return self.__cmd_lib - + @classmethod def can_document_member( cls, @@ -128,7 +128,7 @@ class YosysCmdGroupDocumenter(Documenter): self.content_indent = '' self.fullname = self.modname = self.name return True - + def import_object(self, raiseerror: bool = False) -> bool: # get cmd try: @@ -140,19 +140,19 @@ class YosysCmdGroupDocumenter(Documenter): self.real_modname = self.modname return True - + def get_sourcename(self) -> str: return self.env.doc2path(self.env.docname) - + def format_name(self) -> str: return self.options.caption or '' def format_signature(self, **kwargs: Any) -> str: return self.modname - + def add_directive_header(self, sig: str) -> None: pass - + def add_content(self, more_content: Any | None) -> None: pass @@ -323,7 +323,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter): return self.object.source_file except AttributeError: return super().get_sourcename() - + def format_name(self) -> str: return self.object.name @@ -347,7 +347,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter): if self.options.noindex: self.add_line(' :noindex:', source_name) - + def add_content(self, more_content: Any | None) -> None: # set sourcename and add content from attribute documentation domain = getattr(self, 'domain', self.objtype) diff --git a/docs/util/custom_directives.py b/docs/util/custom_directives.py index b90584aa7..7072fa1db 100644 --- a/docs/util/custom_directives.py +++ b/docs/util/custom_directives.py @@ -21,7 +21,7 @@ from sphinx.util.nodes import make_refnode from sphinx.util.docfields import Field, GroupedField from sphinx import addnodes -class TocNode(ObjectDescription): +class TocNode(ObjectDescription): def add_target_and_index( self, name: str, @@ -64,7 +64,7 @@ class NodeWithOptions(TocNode): doc_field_types = [ GroupedField('opts', label='Options', names=('option', 'options', 'opt', 'opts')), ] - + def transform_content(self, contentnode: addnodes.desc_content) -> None: """hack `:option -thing: desc` into a proper option list with yoscrypt highlighting""" newchildren = [] @@ -290,7 +290,7 @@ class CellNode(TocNode): self.env.docname, idx, 0)) - + def transform_content(self, contentnode: addnodes.desc_content) -> None: # Add the cell title to the body if 'title' in self.options: @@ -380,7 +380,7 @@ class CellSourceNode(TocNode): # only add target and index entry if this is the first # description of the object with this name in this desc block self.add_target_and_index(name, sig, signode) - + # handle code code = '\n'.join(self.content) literal: Element = nodes.literal_block(code, code) @@ -420,11 +420,11 @@ class CellGroupNode(TocNode): class TagIndex(Index): """A custom directive that creates a tag matrix.""" - + name = 'tag' localname = 'Tag Index' shortname = 'Tag' - + def __init__(self, *args, **kwargs): super(TagIndex, self).__init__(*args, **kwargs) @@ -458,14 +458,14 @@ class TagIndex(Index): objs = {name: (dispname, typ, docname, anchor) for name, dispname, typ, docname, anchor, prio in self.domain.get_objects()} - + tmap = {} tags = self.domain.data[f'obj2{self.name}'] for name, tags in tags.items(): for tag in tags: tmap.setdefault(tag,[]) tmap[tag].append(name) - + for tag in tmap.keys(): lis = content.setdefault(tag, []) objlis = tmap[tag] @@ -480,11 +480,11 @@ class TagIndex(Index): return (ret, True) -class CommandIndex(Index): +class CommandIndex(Index): name = 'cmd' localname = 'Command Reference' shortname = 'Command' - + def __init__(self, *args, **kwargs): super(CommandIndex, self).__init__(*args, **kwargs) @@ -525,7 +525,7 @@ class CommandIndex(Index): lis.append(( dispname, 0, docname, anchor, - '', '', title + '', '', title )) ret = [(k, v) for k, v in sorted(content.items())] @@ -538,7 +538,7 @@ class CellIndex(CommandIndex): class PropIndex(TagIndex): """A custom directive that creates a properties matrix.""" - + name = 'prop' localname = 'Property Index' shortname = 'Prop' @@ -659,7 +659,7 @@ class CommandDomain(Domain): else: print(f"Missing ref for {target} in {fromdocname} ") return None - + class CellDomain(CommandDomain): name = 'cell' label = 'Yosys internal cells' @@ -730,8 +730,8 @@ def setup(app: Sphinx): ('cell-prop', '') app.add_role('autoref', autoref) - + return { - 'version': '0.3', + 'version': '0.3', 'parallel_read_safe': False, } diff --git a/examples/intel/asicworld_lfsr/lfsr_updown.v b/examples/intel/asicworld_lfsr/lfsr_updown.v index 43db1606a..e60012c99 100644 --- a/examples/intel/asicworld_lfsr/lfsr_updown.v +++ b/examples/intel/asicworld_lfsr/lfsr_updown.v @@ -10,7 +10,7 @@ overflow // Overflow output input clk; input reset; - input enable; + input enable; input up_down; output [7 : 0] count; @@ -18,11 +18,11 @@ overflow // Overflow output reg [7 : 0] count; - assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : + assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : (count == {1'b1, {7{1'b0}}}) ; always @(posedge clk) - if (reset) + if (reset) count <= {7{1'b0}}; else if (enable) begin if (up_down) begin diff --git a/examples/intel/asicworld_lfsr/lfsr_updown_tb.v b/examples/intel/asicworld_lfsr/lfsr_updown_tb.v index db29e60f1..65681801c 100644 --- a/examples/intel/asicworld_lfsr/lfsr_updown_tb.v +++ b/examples/intel/asicworld_lfsr/lfsr_updown_tb.v @@ -31,4 +31,4 @@ lfsr_updown U( .overflow ( overflow ) ); -endmodule +endmodule diff --git a/examples/smtbmc/glift/C7552.v b/examples/smtbmc/glift/C7552.v index 47a8b0d37..1dff5338e 100644 --- a/examples/smtbmc/glift/C7552.v +++ b/examples/smtbmc/glift/C7552.v @@ -1,428 +1,428 @@ -module C7552_lev2(pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, - pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, - pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, - pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, - pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, - pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, - pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, - pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, - pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, - pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, - pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, - pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, - pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, - pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, - pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, - pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, - pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, - pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, - pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, - pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, - pi200, pi201, pi202, pi203, pi204, pi205, pi206, po000, po001, po002, - po003, po004, po005, po006, po007, po008, po009, po010, po011, po012, - po013, po014, po015, po016, po017, po018, po019, po020, po021, po022, - po023, po024, po025, po026, po027, po028, po029, po030, po031, po032, - po033, po034, po035, po036, po037, po038, po039, po040, po041, po042, - po043, po044, po045, po046, po047, po048, po049, po050, po051, po052, - po053, po054, po055, po056, po057, po058, po059, po060, po061, po062, - po063, po064, po065, po066, po067, po068, po069, po070, po071, po072, - po073, po074, po075, po076, po077, po078, po079, po080, po081, po082, - po083, po084, po085, po086, po087, po088, po089, po090, po091, po092, - po093, po094, po095, po096, po097, po098, po099, po100, po101, po102, +module C7552_lev2(pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, + pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, + pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, + pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, + pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, + pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, + pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, + pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, + pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, + pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, + pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, + pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, + pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, + pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, + pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, + pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, + pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, + pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, + pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, + pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, + pi200, pi201, pi202, pi203, pi204, pi205, pi206, po000, po001, po002, + po003, po004, po005, po006, po007, po008, po009, po010, po011, po012, + po013, po014, po015, po016, po017, po018, po019, po020, po021, po022, + po023, po024, po025, po026, po027, po028, po029, po030, po031, po032, + po033, po034, po035, po036, po037, po038, po039, po040, po041, po042, + po043, po044, po045, po046, po047, po048, po049, po050, po051, po052, + po053, po054, po055, po056, po057, po058, po059, po060, po061, po062, + po063, po064, po065, po066, po067, po068, po069, po070, po071, po072, + po073, po074, po075, po076, po077, po078, po079, po080, po081, po082, + po083, po084, po085, po086, po087, po088, po089, po090, po091, po092, + po093, po094, po095, po096, po097, po098, po099, po100, po101, po102, po103, po104, po105, po106, po107); -input pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, - pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, - pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, - pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, - pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, - pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, - pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, - pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, - pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, - pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, - pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, - pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, - pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, - pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, - pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, - pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, - pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, - pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, - pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, - pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, +input pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, + pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, + pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, + pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, + pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, + pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, + pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, + pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, + pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, + pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, + pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, + pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, + pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, + pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, + pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, + pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, + pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, + pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, + pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, + pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, pi200, pi201, pi202, pi203, pi204, pi205, pi206; -output po000, po001, po002, po003, po004, po005, po006, po007, po008, po009, - po010, po011, po012, po013, po014, po015, po016, po017, po018, po019, - po020, po021, po022, po023, po024, po025, po026, po027, po028, po029, - po030, po031, po032, po033, po034, po035, po036, po037, po038, po039, - po040, po041, po042, po043, po044, po045, po046, po047, po048, po049, - po050, po051, po052, po053, po054, po055, po056, po057, po058, po059, - po060, po061, po062, po063, po064, po065, po066, po067, po068, po069, - po070, po071, po072, po073, po074, po075, po076, po077, po078, po079, - po080, po081, po082, po083, po084, po085, po086, po087, po088, po089, - po090, po091, po092, po093, po094, po095, po096, po097, po098, po099, +output po000, po001, po002, po003, po004, po005, po006, po007, po008, po009, + po010, po011, po012, po013, po014, po015, po016, po017, po018, po019, + po020, po021, po022, po023, po024, po025, po026, po027, po028, po029, + po030, po031, po032, po033, po034, po035, po036, po037, po038, po039, + po040, po041, po042, po043, po044, po045, po046, po047, po048, po049, + po050, po051, po052, po053, po054, po055, po056, po057, po058, po059, + po060, po061, po062, po063, po064, po065, po066, po067, po068, po069, + po070, po071, po072, po073, po074, po075, po076, po077, po078, po079, + po080, po081, po082, po083, po084, po085, po086, po087, po088, po089, + po090, po091, po092, po093, po094, po095, po096, po097, po098, po099, po100, po101, po102, po103, po104, po105, po106, po107; -wire n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, - n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, - n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, - n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, - n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, - n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, - n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, - n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, - n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, - n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, - n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, - n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, - n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, - n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, - n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, - n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, - n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, - n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, - n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, - n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, - n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, - n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, - n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, - n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, - n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, - n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, - n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, - n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, - n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, - n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, - n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, - n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, - n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, - n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, - n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, - n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, - n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, - n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, - n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, - n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, - n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, - n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, - n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, - n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, - n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, - n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, - n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, - n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, - n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, - n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, - n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, - n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, - n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, - n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, - n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, - n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, - n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, - n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, - n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, - n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, - n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, - n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, - n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, - n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, - n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, - n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, - n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, - n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, - n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, - n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, - n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, - n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, - n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, - n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, - n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, - n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, - n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, - n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, - n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, - n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, - n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, - n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, - n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, - n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, - n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, - n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, - n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, - n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, - n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, - n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, - n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, - n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, - n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, - n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, - n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, - n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, - n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, - n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, - n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, - n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, - n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, - n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, - n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, - n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, - n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, - n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, - n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, - n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, - n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, - n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, - n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, - n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, - n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, - n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, - n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, - n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, - n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, - n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, - n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, - n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, - n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, - n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, - n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, - n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, - n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, - n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, - n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, - n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, - n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, - n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, - n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, - n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, - n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, - n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, - n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, - n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, - n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, - n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, - n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, - n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, - n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, - n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, - n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, - n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, - n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, - n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, - n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, - n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, - n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, - n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, - n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, - n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, - n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, - n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, - n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, - n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, - n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, - n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, - n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, - n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, - n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, - n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, - n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, - n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, - n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, - n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, - n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, - n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, - n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, - n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, - n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, - n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, - n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, - n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, - n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, - n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, - n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, - n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, - n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, - n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, - n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, - n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, - n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, - n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, - n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, - n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, - n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, - n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, - n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, - n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, - n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, - n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, - n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, - n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, - n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, - n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, - n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, - n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, - n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, - n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, - n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, - n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, - n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, - n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, - n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, - n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, - n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, - n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, - n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, - n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, - n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, - n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, - n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, - n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, - n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, - n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, - n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, - n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, - n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, - n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, - n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, - n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, - n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, - n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, - n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, - n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, - n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, - n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, - n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, - n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, - n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, - n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, - n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, - n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, - n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, - n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, - n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, - n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, - n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, - n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, - n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, - n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, - n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, - n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, - n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, - n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, - n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, - n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, - n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, - n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, - n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, - n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, - n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, - n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, - n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, - n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, - n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, - n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, - n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, - n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, - n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, - n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, - n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, - n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, - n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, - n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, - n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, - n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, - n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, - n5512, n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, - n5522, n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, - n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, - n5542, n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, - n5552, n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, - n5562, n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, - n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, - n5582, n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, - n5592, n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, - n5602, n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, - n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, - n5622, n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, - n5632, n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, - n5642, n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, - n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, - n5662, n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, - n5672, n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, - n5682, n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, - n5692, n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, - n5702, n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, - n5712, n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, - n5722, n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, - n5732, n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, - n5742, n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, - n5752, n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, - n5762, n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, - n5772, n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, - n5782, n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, - n5792, n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, - n5802, n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, - n5812, n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, - n5822, n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, - n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, - n5842, n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, - n5852, n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, - n5862, n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, - n5872, n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, - n5882, n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, - n5892, n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, - n5902, n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, - n5912, n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, - n5922, n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, - n5932, n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, - n5942, n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, - n5952, n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, - n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, - n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, - n5982, n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, - n5992, n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, - n6002, n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, - n6012, n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, - n6022, n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, - n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, - n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, - n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, - n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, - n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, - n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, - n6092, n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, - n6102, n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, - n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, - n6122, n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, - n6132, n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, - n6142, n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, - n6152, n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, - n6162, n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, - n6172, n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, - n6182, n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, - n6192, n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, - n6202, n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, - n6212, n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, - n6222, n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, - n6232, n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, - n6242, n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, - n6252, n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, - n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, - n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, - n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, - n6292, n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, - n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, - n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, - n6322, n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, - n6332, n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, - n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, - n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, - n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, - n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, - n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, - n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, +wire n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, + n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, + n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, + n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, + n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, + n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, + n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, + n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, + n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, + n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, + n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, + n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, + n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, + n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, + n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, + n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, + n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, + n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, + n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, + n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, + n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, + n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, + n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, + n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, + n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, + n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, + n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, + n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, + n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, + n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, + n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, + n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, + n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, + n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, + n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, + n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, + n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, + n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, + n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, + n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, + n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, + n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, + n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, + n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, + n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, + n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, + n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, + n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, + n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, + n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, + n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, + n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, + n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, + n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, + n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, + n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, + n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, + n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, + n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, + n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, + n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, + n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, + n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, + n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, + n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, + n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, + n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, + n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, + n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, + n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, + n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, + n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, + n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, + n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, + n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, + n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, + n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, + n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, + n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, + n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, + n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, + n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, + n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, + n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, + n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, + n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, + n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, + n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, + n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, + n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, + n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, + n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, + n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, + n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, + n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, + n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, + n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, + n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, + n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, + n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, + n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, + n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, + n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, + n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, + n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, + n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, + n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, + n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, + n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, + n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, + n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, + n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, + n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, + n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, + n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, + n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, + n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, + n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, + n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, + n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, + n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, + n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, + n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, + n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, + n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, + n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, + n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, + n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, + n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, + n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, + n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, + n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, + n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, + n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, + n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, + n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, + n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, + n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, + n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, + n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, + n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, + n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, + n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, + n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, + n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, + n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, + n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, + n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, + n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, + n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, + n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, + n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, + n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, + n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, + n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, + n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, + n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, + n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, + n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, + n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, + n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, + n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, + n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, + n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, + n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, + n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, + n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, + n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, + n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, + n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, + n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, + n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, + n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, + n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, + n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, + n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, + n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, + n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, + n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, + n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, + n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, + n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, + n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, + n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, + n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, + n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, + n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, + n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, + n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, + n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, + n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, + n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, + n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, + n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, + n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, + n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, + n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, + n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, + n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, + n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, + n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, + n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, + n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, + n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, + n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, + n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, + n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, + n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, + n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, + n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, + n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, + n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, + n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, + n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, + n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, + n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, + n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, + n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, + n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, + n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, + n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, + n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, + n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, + n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, + n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, + n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, + n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, + n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, + n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, + n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, + n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, + n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, + n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, + n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, + n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, + n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, + n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, + n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, + n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, + n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, + n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, + n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, + n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, + n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, + n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, + n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, + n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, + n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, + n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, + n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, + n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, + n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, + n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, + n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, + n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, + n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, + n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, + n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, + n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, + n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, + n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, + n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, + n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, + n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, + n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, + n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, + n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, + n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, + n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, + n5512, n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, + n5522, n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, + n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, + n5542, n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, + n5552, n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, + n5562, n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, + n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, + n5582, n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, + n5592, n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, + n5602, n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, + n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, + n5622, n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, + n5632, n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, + n5642, n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, + n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, + n5662, n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, + n5672, n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, + n5682, n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, + n5692, n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, + n5702, n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, + n5712, n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, + n5722, n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, + n5732, n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, + n5742, n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, + n5752, n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, + n5762, n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, + n5772, n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, + n5782, n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, + n5792, n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, + n5802, n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, + n5812, n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, + n5822, n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, + n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, + n5842, n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, + n5852, n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, + n5862, n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, + n5872, n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, + n5882, n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, + n5892, n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, + n5902, n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, + n5912, n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, + n5922, n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, + n5932, n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, + n5942, n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, + n5952, n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, + n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, + n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, + n5982, n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, + n5992, n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, + n6002, n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, + n6012, n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, + n6022, n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, + n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, + n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, + n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, + n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, + n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, + n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, + n6092, n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, + n6102, n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, + n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, + n6122, n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, + n6132, n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, + n6142, n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, + n6152, n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, + n6162, n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, + n6172, n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, + n6182, n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, + n6192, n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, + n6202, n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, + n6212, n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, + n6222, n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, + n6232, n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, + n6242, n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, + n6252, n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, + n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, + n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, + n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, + n6292, n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, + n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, + n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, + n6322, n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, + n6332, n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, + n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, + n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, + n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, + n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, + n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, + n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405; assign po001 = pi187; diff --git a/examples/smtbmc/glift/C7552.ys b/examples/smtbmc/glift/C7552.ys index a9a1f5dc2..dcae30e85 100644 --- a/examples/smtbmc/glift/C7552.ys +++ b/examples/smtbmc/glift/C7552.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/C880.v b/examples/smtbmc/glift/C880.v index 20e665f4a..799c02ddf 100644 --- a/examples/smtbmc/glift/C880.v +++ b/examples/smtbmc/glift/C880.v @@ -1,58 +1,58 @@ -module C880_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, - pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59, - po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, +module C880_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, + pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59, + po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20, po21, po22, po23, po24, po25); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59; -output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, +output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20, po21, po22, po23, po24, po25; -wire n137, n346, n364, n415, n295, n427, n351, n377, n454, n357, - n358, n359, n360, n361, n362, n363, n365, n366, n367, n368, - n369, n370, n371, n372, n373, n374, n375, n376, n378, n379, - n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, - n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, - n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, - n410, n411, n412, n413, n414, n416, n417, n418, n419, n420, - n421, n422, n423, n424, n425, n426, n428, n429, n430, n431, - n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, - n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, - n452, n453, n455, n456, n457, n458, n459, n460, n461, n462, - n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, - n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, - n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, - n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, - n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, - n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, - n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, - n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, - n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, - n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, - n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, - n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, - n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, - n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, - n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, - n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, - n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, - n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, - n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, - n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, - n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, - n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, - n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, +wire n137, n346, n364, n415, n295, n427, n351, n377, n454, n357, + n358, n359, n360, n361, n362, n363, n365, n366, n367, n368, + n369, n370, n371, n372, n373, n374, n375, n376, n378, n379, + n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, + n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, + n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, + n410, n411, n412, n413, n414, n416, n417, n418, n419, n420, + n421, n422, n423, n424, n425, n426, n428, n429, n430, n431, + n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, + n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, + n452, n453, n455, n456, n457, n458, n459, n460, n461, n462, + n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, + n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, + n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, + n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, + n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, + n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, + n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, + n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, + n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, + n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, + n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, + n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, + n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, + n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, + n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, + n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, + n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, + n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, + n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, + n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, + n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, + n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, + n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696; diff --git a/examples/smtbmc/glift/C880.ys b/examples/smtbmc/glift/C880.ys index 410768f21..37b568da1 100644 --- a/examples/smtbmc/glift/C880.ys +++ b/examples/smtbmc/glift/C880.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/alu2.v b/examples/smtbmc/glift/alu2.v index 6b6e3d7af..ac2b2b10c 100644 --- a/examples/smtbmc/glift/alu2.v +++ b/examples/smtbmc/glift/alu2.v @@ -1,42 +1,42 @@ -module alu2_lev2(pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9, +module alu2_lev2(pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9, po0, po1, po2, po3, po4, po5); input pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9; output po0, po1, po2, po3, po4, po5; -wire n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, - n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, - n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, - n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, - n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, - n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, - n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, - n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, - n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, - n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, - n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, - n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, - n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, - n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, - n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, - n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, - n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, - n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, - n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, - n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, - n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, - n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, - n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, - n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, - n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, - n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, - n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, - n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, - n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, - n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, - n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, - n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, +wire n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, + n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, + n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, + n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, + n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, + n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, + n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, + n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, + n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, + n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, + n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, + n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, + n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, + n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, + n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, + n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, + n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, + n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, + n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, + n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, + n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, + n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, + n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, + n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, + n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, + n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, + n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, + n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, + n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, + n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, + n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, + n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687; AN2 U363 ( .A(n358), .B(po2), .Z(po5)); diff --git a/examples/smtbmc/glift/alu2.ys b/examples/smtbmc/glift/alu2.ys index b1671752e..f43dad075 100644 --- a/examples/smtbmc/glift/alu2.ys +++ b/examples/smtbmc/glift/alu2.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/alu4.v b/examples/smtbmc/glift/alu4.v index e110612e5..bc221eb04 100644 --- a/examples/smtbmc/glift/alu4.v +++ b/examples/smtbmc/glift/alu4.v @@ -1,80 +1,80 @@ -module alu4_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +module alu4_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13, po0, po1, po2, po3, po4, po5, po6, po7); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13; output po0, po1, po2, po3, po4, po5, po6, po7; -wire n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, - n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, - n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, - n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, - n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, - n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, - n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, - n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, - n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, - n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, - n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, - n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, - n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, - n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, - n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, - n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, - n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, - n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, - n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, - n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, - n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, - n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, - n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, - n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, - n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, - n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, - n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, - n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, - n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, - n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, - n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, - n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, - n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, - n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, - n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, - n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, - n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, - n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, - n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, - n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, - n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, - n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, - n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, - n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, - n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, - n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, - n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, - n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, - n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, - n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, - n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, - n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, - n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, - n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, - n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, - n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, - n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, - n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, - n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, - n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, - n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, - n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, - n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, - n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, - n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, - n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, - n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, - n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, - n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, +wire n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, + n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, + n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, + n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, + n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, + n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, + n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, + n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, + n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, + n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, + n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, + n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, + n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, + n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, + n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, + n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, + n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, + n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, + n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, + n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, + n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, + n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, + n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, + n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, + n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, + n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, + n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, + n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, + n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, + n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, + n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, + n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, + n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, + n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, + n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, + n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, + n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, + n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, + n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, + n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, + n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, + n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, + n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, + n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, + n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, + n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, + n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, + n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, + n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, + n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, + n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, + n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, + n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, + n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, + n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, + n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, + n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, + n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, + n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, + n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, + n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, + n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, + n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, + n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, + n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, + n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, + n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, + n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, + n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396; AN2 U712 ( .A(n705), .B(po4), .Z(po7)); diff --git a/examples/smtbmc/glift/alu4.ys b/examples/smtbmc/glift/alu4.ys index 8e8d14225..593ba45a7 100644 --- a/examples/smtbmc/glift/alu4.ys +++ b/examples/smtbmc/glift/alu4.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/t481.v b/examples/smtbmc/glift/t481.v index b23c8b211..6735fc9a9 100644 --- a/examples/smtbmc/glift/t481.v +++ b/examples/smtbmc/glift/t481.v @@ -1,15 +1,15 @@ -module t481_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +module t481_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13, pi14, pi15, po0); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13, pi14, pi15; output po0; -wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, - n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, - n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, - n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, +wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, + n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, + n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, + n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90; OR2 U47 ( .A(n46), .B(n47), .Z(po0)); diff --git a/examples/smtbmc/glift/t481.ys b/examples/smtbmc/glift/t481.ys index 0e4afffda..ac31f8fc1 100644 --- a/examples/smtbmc/glift/t481.ys +++ b/examples/smtbmc/glift/t481.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/too_large.v b/examples/smtbmc/glift/too_large.v index 67605cc34..8392a7a13 100644 --- a/examples/smtbmc/glift/too_large.v +++ b/examples/smtbmc/glift/too_large.v @@ -1,43 +1,43 @@ -module too_large_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, po0, po1, +module too_large_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, po0, po1, po2); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37; output po0, po1, po2; -wire n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, - n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, - n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, - n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, - n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, - n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, - n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, - n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, - n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, - n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, - n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, - n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, - n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, - n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, - n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, - n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, - n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, - n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, - n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, - n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, - n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, - n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, - n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, - n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, - n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, - n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, - n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, +wire n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, + n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, + n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, + n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, + n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, + n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, + n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, + n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, + n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, + n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, + n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, + n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, + n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, + n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, + n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, + n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, + n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, + n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, + n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, + n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, + n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, + n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, + n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, + n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, + n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, + n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, + n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556; AN2 U283 ( .A(n280), .B(n281), .Z(po2)); diff --git a/examples/smtbmc/glift/too_large.ys b/examples/smtbmc/glift/too_large.ys index 77be61e17..ec5edd0ca 100644 --- a/examples/smtbmc/glift/too_large.ys +++ b/examples/smtbmc/glift/too_large.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/ttt2.v b/examples/smtbmc/glift/ttt2.v index 47ca7684a..1c538b917 100644 --- a/examples/smtbmc/glift/ttt2.v +++ b/examples/smtbmc/glift/ttt2.v @@ -1,31 +1,31 @@ -module ttt2_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, po00, po01, po02, po03, po04, po05, - po06, po07, po08, po09, po10, po11, po12, po13, po14, po15, +module ttt2_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, po00, po01, po02, po03, po04, po05, + po06, po07, po08, po09, po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, pi20, pi21, pi22, pi23; -output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, +output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20; -wire n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, - n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, - n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, - n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, - n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, - n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, - n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, - n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, - n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, - n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, - n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, - n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, - n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, - n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, +wire n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, + n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, + n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, + n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, + n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, + n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, + n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, + n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, + n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, + n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, + n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, + n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, + n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, + n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293; AN2 U168 ( .A(n148), .B(n149), .Z(po20)); diff --git a/examples/smtbmc/glift/ttt2.ys b/examples/smtbmc/glift/ttt2.ys index 1314d4975..e1f9e05a8 100644 --- a/examples/smtbmc/glift/ttt2.ys +++ b/examples/smtbmc/glift/ttt2.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/x1.v b/examples/smtbmc/glift/x1.v index 39b5284d3..6b2f51917 100644 --- a/examples/smtbmc/glift/x1.v +++ b/examples/smtbmc/glift/x1.v @@ -1,52 +1,52 @@ -module x1_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, - pi50, po00, po01, po02, po03, po04, po05, po06, po07, po08, - po09, po10, po11, po12, po13, po14, po15, po16, po17, po18, - po19, po20, po21, po22, po23, po24, po25, po26, po27, po28, +module x1_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, + pi50, po00, po01, po02, po03, po04, po05, po06, po07, po08, + po09, po10, po11, po12, po13, po14, po15, po16, po17, po18, + po19, po20, po21, po22, po23, po24, po25, po26, po27, po28, po29, po30, po31, po32, po33, po34); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, pi50; -output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, - po20, po21, po22, po23, po24, po25, po26, po27, po28, po29, +output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, + po20, po21, po22, po23, po24, po25, po26, po27, po28, po29, po30, po31, po32, po33, po34; -wire po05, po16, po18, po24, po25, po28, po29, n270, n271, n272, - n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, - n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, - n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, - n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, - n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, - n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, - n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, - n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, - n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, - n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, - n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, - n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, - n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, - n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, - n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, - n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, - n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, - n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, - n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, - n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, - n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, - n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, - n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, - n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, - n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, - n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, +wire po05, po16, po18, po24, po25, po28, po29, n270, n271, n272, + n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, + n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, + n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, + n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, + n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, + n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, + n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, + n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, + n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, + n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, + n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, + n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, + n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, + n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, + n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, + n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, + n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, + n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, + n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, + n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, + n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, + n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, + n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, + n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, + n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, + n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533; assign po05 = pi32; diff --git a/examples/smtbmc/glift/x1.ys b/examples/smtbmc/glift/x1.ys index b588dea92..406127c10 100644 --- a/examples/smtbmc/glift/x1.ys +++ b/examples/smtbmc/glift/x1.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 20a23ef8f..7beb152cb 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -130,13 +130,13 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (log_verific_callback) { string full_message = stringf("%s%s\n", message_prefix, message); -#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS - log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), - linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, +#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), + linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str()); #else - log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), - linefile ? LineFile::GetLineNo(linefile) : 0, 0, + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), + linefile ? LineFile::GetLineNo(linefile) : 0, 0, linefile ? LineFile::GetLineNo(linefile) : 0, 0, full_message.c_str()); #endif } else { @@ -323,7 +323,7 @@ static const RTLIL::Const extract_vhdl_const(const char *value, bool output_sig bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; }); if (isBinary) c = RTLIL::Const::from_string(data); - else + else c = RTLIL::Const(data); } else if (val.size()==3 && val[0]=='\'' && val.back()=='\'') { c = RTLIL::Const::from_string(val.substr(1,val.size()-2)); @@ -413,7 +413,7 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value // SystemVerilog if (type_name && strcmp(type_name, "real")==0) { return extract_real_value(val); - } else + } else return extract_verilog_const(value, allow_string, output_signed); } @@ -1277,7 +1277,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr for (unsigned j = 0 ; j < selector->GetNumConditions(i) ; ++j) { Array left_bound, right_bound ; selector->GetCondition(i, j, &left_bound, &right_bound); - + SigSpec sel_left = sig_select_values.extract(offset_select, select_width); offset_select += select_width; @@ -1565,7 +1565,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma char *architecture_name = name_space.ReName(nl->Name()) ; module->set_string_attribute(ID(architecture), (architecture_name) ? architecture_name : nl->Name()); } -#endif +#endif const char *param_name ; const char *param_value ; MapIter mi; @@ -2827,13 +2827,13 @@ void save_blackbox_msg_state() void restore_blackbox_msg_state() { #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - Message::ClearMessageType("VERI-1063") ; + Message::ClearMessageType("VERI-1063") ; if (Message::GetMessageType("VERI-1063")!=prev_1063) Message::SetMessageType("VERI-1063", prev_1063); #endif #ifdef VERIFIC_VHDL_SUPPORT - Message::ClearMessageType("VHDL-1240") ; - Message::ClearMessageType("VHDL-1241") ; + Message::ClearMessageType("VHDL-1240") ; + Message::ClearMessageType("VHDL-1241") ; if (Message::GetMessageType("VHDL-1240")!=prev_1240) Message::SetMessageType("VHDL-1240", prev_1240); if (Message::GetMessageType("VHDL-1241")!=prev_1241) @@ -3414,7 +3414,7 @@ struct VerificPass : public Pass { log("\n"); #if defined(YOSYS_ENABLE_VERIFIC) and defined(YOSYSHQ_VERIFIC_EXTENSIONS) VerificExtensions::Help(); -#endif +#endif log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"); log("https://www.yosyshq.com/\n"); log("\n"); @@ -3470,7 +3470,7 @@ struct VerificPass : public Pass { VhdlPrimaryUnit *unit ; if (!flag_lib) return; VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); - if (vhdl_lib) { + if (vhdl_lib) { FOREACH_VHDL_PRIMARY_UNIT(vhdl_lib, mi, unit) { if (!unit) continue; map.Insert(unit,unit); @@ -3502,7 +3502,7 @@ struct VerificPass : public Pass { VeriModule *veri_module ; if (!flag_lib) return; VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); - if (veri_lib) { + if (veri_lib) { FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { if (!veri_module) continue; map.Insert(veri_module,veri_module); @@ -4433,12 +4433,12 @@ struct VerificPass : public Pass { } } #ifdef YOSYSHQ_VERIFIC_EXTENSIONS - if (VerificExtensions::Execute(args, argidx, work, + if (VerificExtensions::Execute(args, argidx, work, [this](const std::vector &args, size_t argidx, std::string msg) { cmd_error(args, argidx, msg); } )) { goto check_error; } -#endif +#endif cmd_error(args, argidx, "Missing or unsupported mode parameter.\n"); diff --git a/kernel/cellhelp.py b/kernel/cellhelp.py index f834ead83..a92922fe6 100644 --- a/kernel/cellhelp.py +++ b/kernel/cellhelp.py @@ -19,7 +19,7 @@ class SimHelper: def __init__(self) -> None: self.desc = [] self.tags = [] - + def __str__(self) -> str: printed_fields = [ "name", "title", "ports", "source", "desc", "code", "group", "ver", @@ -65,7 +65,7 @@ for line in fileinput.input(): elif line.startswith("//* "): _, key, val = line.split(maxsplit=2) setattr(simHelper, key, val) - + # code parsing if line.startswith("module "): clean_line = line[7:].replace("\\", "").replace(";", "") diff --git a/kernel/compressor_tree.cc b/kernel/compressor_tree.cc index de2260d26..b02a8fd5c 100644 --- a/kernel/compressor_tree.cc +++ b/kernel/compressor_tree.cc @@ -99,7 +99,7 @@ std::vector generate_partial_products(Module *module, SigSpec a, SigSp // Correction constants auto push_one_at = [&](int col) { - if (col < 0 || col >= width) + if (col < 0 || col >= width) return; std::vector v(width, RTLIL::State::S0); v[col] = RTLIL::State::S1; diff --git a/kernel/functional.h b/kernel/functional.h index 3334f02c8..6d98da949 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -33,7 +33,7 @@ YOSYS_NAMESPACE_BEGIN namespace Functional { // each function is documented with a short pseudocode declaration or definition // standard C/Verilog operators are used to describe the result - // + // // the sorts used in this are: // - bit[N]: a bitvector of N bits // bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend @@ -345,9 +345,9 @@ namespace Functional { case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break; case Fn::equal: return v.equal(*this, arg(0), arg(1)); break; case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break; - case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; + case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break; - case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; + case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break; case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break; case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break; @@ -510,7 +510,7 @@ namespace Functional { return a; return add(Fn::reduce_or, Sort(1), {a}); } - Node reduce_xor(Node a) { + Node reduce_xor(Node a) { check_unary(a); if(a.width() == 1) return a; diff --git a/kernel/io.h b/kernel/io.h index e15194e79..f80b9e908 100644 --- a/kernel/io.h +++ b/kernel/io.h @@ -202,7 +202,7 @@ static auto has_name_member_imp(int) -> decltype(static_cast(std::declval().name), std::true_type{}); template -static auto has_name_member_imp(long) +static auto has_name_member_imp(long) -> std::false_type; template @@ -213,7 +213,7 @@ static auto ptr_has_name_member_imp(int) -> decltype(static_cast(std::declval()->name), std::true_type{}); template -static auto ptr_has_name_member_imp(long) +static auto ptr_has_name_member_imp(long) -> std::false_type; template @@ -475,7 +475,7 @@ public: private: std::string_view fmt; bool has_escapes = false; - // Making array at least size of one to make MSVC happy and strict to standards + // Making array at least size of one to make MSVC happy and strict to standards FoundFormatSpec specs[sizeof...(Args) ? sizeof...(Args) : 1] = {}; }; diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index 2479b7e3c..70d587904 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -567,7 +567,7 @@ int yosys_tcl_interp_init(Tcl_Interp *interp) // unpack // pack - // Note (dev jf 24-12-02): Make log_id escape everything that’s not a valid + // Note (dev jf 24-12-02): Make log_id escape everything that’s not a valid // verilog identifier before adding any tcl API that returns IdString values // to avoid -option injection diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h index 7e730bb27..6b4ffc1e2 100644 --- a/kernel/topo_scc.h +++ b/kernel/topo_scc.h @@ -241,7 +241,7 @@ public: } // process all remaining nodes in the graph - TopoSortedSccs &process_all() { + TopoSortedSccs &process_all() { node_enumerator nodes = graph.enumerate_nodes(); // iterate over all nodes to ensure we process the whole graph while (!nodes.finished()) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 426216800..d219f8da3 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -217,7 +217,7 @@ struct CheckPass : public Pass { const int threshold = 1024; - // if the multiplication may overflow we will catch it here + // if the multiplication may overflow we will catch it here if (in_widths + out_widths >= threshold) return true; @@ -400,7 +400,7 @@ struct CheckPass : public Pass { message += stringf(" cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src); - if (!coarsened_cells.count(driver)) { + if (!coarsened_cells.count(driver)) { MatchingEdgePrinter printer(message, sigmap, prev, bit); printer.add_edges_from_cell(driver); } else { @@ -414,7 +414,7 @@ struct CheckPass : public Pass { std::string src_attr = wire->get_src_attribute(); wire_src = stringf(" source: %s", src_attr); } - message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src); + message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src); } prev = bit; diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc index 2f77f6f21..a65667f38 100644 --- a/passes/cmds/linecoverage.cc +++ b/passes/cmds/linecoverage.cc @@ -90,7 +90,7 @@ struct CoveragePass : public Pass { std::map> uncovered_lines; std::map> all_lines; - + for (auto module : design->modules()) { log_debug("Module %s:\n", module); @@ -136,7 +136,7 @@ struct CoveragePass : public Pass { fout << "DA:" << l << ","; if (uncovered_lines.count(file_entry.first) && uncovered_lines[file_entry.first].count(l)) fout << "0"; - else + else fout << "1"; fout << "\n"; } diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc index 2b75a3a79..bbe23c9e5 100644 --- a/passes/cmds/linux_perf.cc +++ b/passes/cmds/linux_perf.cc @@ -36,7 +36,7 @@ struct LinuxPerf : public Pass { bool formatted_help() override { auto *help = PrettyHelp::get_current(); - + auto content_root = help->get_root(); content_root->usage("linux_perf [on|off]"); diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index cab4ab81c..4d75b3872 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -106,7 +106,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-warn" && argidx+1 < args.size()) { std::string pattern = args[++argidx]; - if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { log("Added regex '%s' for warnings to warn list.\n", pattern); log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern)); @@ -118,7 +118,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-nowarn" && argidx+1 < args.size()) { std::string pattern = args[++argidx]; - if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { log("Added regex '%s' for warnings to nowarn list.\n", pattern); log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern)); @@ -130,7 +130,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-werror" && argidx+1 < args.size()) { std::string pattern = args[++argidx]; - if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { log("Added regex '%s' for warnings to werror list.\n", pattern); log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern)); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 1fcc35dfa..76b323338 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1472,7 +1472,7 @@ struct SelectPass : public Pass { const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min"; if (common_flagset_tally > 1) - log_cmd_error("Options %s can not be combined.\n", common_flagset); + log_cmd_error("Options %s can not be combined.\n", common_flagset); if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally) log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset); diff --git a/passes/cmds/setenv.cc b/passes/cmds/setenv.cc index 90eeab702..bb071b271 100644 --- a/passes/cmds/setenv.cc +++ b/passes/cmds/setenv.cc @@ -47,14 +47,14 @@ struct SetenvPass : public Pass { std::string name = args[1]; std::string value = args[2]; if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2); - + #if defined(_WIN32) _putenv_s(name.c_str(), value.c_str()); #else if (setenv(name.c_str(), value.c_str(), 1)) log_cmd_error("Invalid name \"%s\".\n", name); #endif - + } } SetenvPass; diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index 579a9c48e..80843aaee 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -122,7 +122,7 @@ struct EstimateSta { if (aigs.at(fingerprint).name.empty()) { log_error("Unsupported cell '%s' in module '%s'", cell->type.unescape(), m); - } + } } combinational.push_back(cell); @@ -217,9 +217,9 @@ struct EstimateSta { if (!topo.sort()) log_error("Module '%s' contains combinational loops", m); - + // now we determine how long it takes for signals to stabilize - + // `levels` records the time after a clock edge after which a signal is stable dict, arrivalint> levels; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index a7be16577..7d7091c42 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -343,7 +343,7 @@ struct MemMapping { rejected_cfg_debug_msgs += "\n"; } } - + void log_reject(const Ram &ram, const PortGroup &pg, int pvi, std::string message) { if(ys_debug(1)) { rejected_cfg_debug_msgs += stringf("can't map to option selection ["); @@ -516,7 +516,7 @@ std::pair search_for_attribute(Mem mem, IdString attr) { for (SigBit bit: port.addr) if (bit.is_wire() && bit.wire->has_attribute(attr)) return std::make_pair(true, bit.wire->attributes.at(attr)); - + return std::make_pair(false, Const()); } diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 773bbfde9..f78da20c0 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -159,7 +159,7 @@ struct MuxpackWorker if (cell->type == ID($mux)) b_sig = sigmap(cell->getPort(ID::B)); SigSpec y_sig = sigmap(cell->getPort(ID::Y)); - + if (sig_chain_next.count(a_sig)) for (auto a_bit : a_sig) sigbit_with_non_chain_users.insert(a_bit); diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 98d5b9928..915a6fb39 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -73,15 +73,15 @@ struct OptBalanceTreeWorker { // Base case: if we have only one source, return it if (sources.size() == 1) return sources[0]; - + // Base case: if we have two sources, create a single cell if (sources.size() == 2) { // Create a new cell of the same type Cell* new_cell = module->addCell(NEW_ID, cell_type); - + // Copy attributes from reference cell new_cell->attributes = cell->attributes; - + // Create output wire int out_width = cell->getParam(ID::Y_WIDTH).as_int(); if (cell_type == ID($add)) @@ -89,7 +89,7 @@ struct OptBalanceTreeWorker { else if (cell_type == ID($mul)) out_width = sources[0].size() + sources[1].size(); Wire* out_wire = module->addWire(NEW_ID, out_width); - + // Connect ports and fix up parameters new_cell->setPort(ID::A, sources[0]); new_cell->setPort(ID::B, sources[1]); @@ -97,26 +97,26 @@ struct OptBalanceTreeWorker { new_cell->fixup_parameters(); new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); - + // Update count and return output wire cell_count[cell_type]++; return out_wire; } - + // Recursive case: split sources into two groups and create subtrees int mid = (sources.size() + 1) / 2; vector left_sources(sources.begin(), sources.begin() + mid); vector right_sources(sources.begin() + mid, sources.end()); - + SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell); SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell); - + // Create a cell to combine the two subtrees Cell* new_cell = module->addCell(NEW_ID, cell_type); - + // Copy attributes from reference cell new_cell->attributes = cell->attributes; - + // Create output wire int out_width = cell->getParam(ID::Y_WIDTH).as_int(); if (cell_type == ID($add)) @@ -124,7 +124,7 @@ struct OptBalanceTreeWorker { else if (cell_type == ID($mul)) out_width = left_tree.size() + right_tree.size(); Wire* out_wire = module->addWire(NEW_ID, out_width); - + // Connect ports and fix up parameters new_cell->setPort(ID::A, left_tree); new_cell->setPort(ID::B, right_tree); @@ -132,7 +132,7 @@ struct OptBalanceTreeWorker { new_cell->fixup_parameters(); new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); - + // Update count and return output wire cell_count[cell_type]++; return out_wire; @@ -280,7 +280,7 @@ struct OptBalanceTreeWorker { { // Create a tree log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", head_cell, GetSize(sources), inner_cells); - + // Build a vector of all source signals vector source_signals; vector signed_flags; @@ -295,10 +295,10 @@ struct OptBalanceTreeWorker { if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) { continue; } - + // Create the balanced tree SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell); - + // Connect the tree output to the head cell's output SigSpec head_output = sigmap(head_cell->getPort(ID::Y)); int connect_width = std::min(head_output.size(), tree_output.size()); @@ -313,7 +313,7 @@ struct OptBalanceTreeWorker { } } } - + // Remove all consumed cells, which now have been replaced by trees for (auto cell : consumed_cells) module->remove(cell); diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc index 532bcad63..878ccfe0a 100644 --- a/passes/opt/opt_hier.cc +++ b/passes/opt/opt_hier.cc @@ -75,7 +75,7 @@ struct ModuleIndex { } else { classes[pair.second[i]].append(pair.first[i]); } - } + } } } @@ -217,7 +217,7 @@ struct UsageData { for (auto port_name : module->ports) { Wire *port = module->wire(port_name); log_assert(port); - + if (port->port_input && port->port_output) { // ignore bidirectional: hard to come up with sound handling continue; diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 72c465ead..039c02d7d 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -296,7 +296,7 @@ struct OptLutWorker luts_dlogic_inputs.erase(lut); module->remove(lut); - + eliminated_count++; if (limit > 0) limit--; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index b213048aa..1836806cc 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -445,7 +445,7 @@ struct OptSharePass : public Pass { while (mux_port_offset + op_conn_width < mux_port_size && op_outsig_offset + op_conn_width < op_outsig_size && mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width]) - op_conn_width++; + op_conn_width++; log_assert(op_conn_width >= 1); diff --git a/passes/opt/peepopt_muldiv_c.pmg b/passes/opt/peepopt_muldiv_c.pmg index eb8b31e13..a0b10d584 100644 --- a/passes/opt/peepopt_muldiv_c.pmg +++ b/passes/opt/peepopt_muldiv_c.pmg @@ -55,19 +55,19 @@ code int c_const_int = c_const.as_int(c_const_signed); int b_const_int_shifted = b_const_int << offset; - // Helper lambdas for two's complement math + // Helper lambdas for two's complement math auto sign2sComplement = [](auto value, int numBits) { if (value & (1 << (numBits - 1))) { - return -1; + return -1; } else { - return 1; + return 1; } }; auto twosComplement = [](auto value, int numBits) { if (value & (1 << (numBits - 1))) { return (~value) + 1; // invert bits before adding 1 } else { - return value; + return value; } }; diff --git a/passes/opt/peepopt_shiftadd.pmg b/passes/opt/peepopt_shiftadd.pmg index 6144e44ef..622516062 100644 --- a/passes/opt/peepopt_shiftadd.pmg +++ b/passes/opt/peepopt_shiftadd.pmg @@ -104,8 +104,8 @@ code std::string location = shift->get_src_attribute(); if(shiftadd_max_ratio>0 && offset<0 && -offset*shiftadd_max_ratio > old_a.size()) { - log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) " - "was ignored to avoid high resource usage, see help peepopt\n", + log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) " + "was ignored to avoid high resource usage, see help peepopt\n", location.c_str(), log_signal(old_a), log_signal(var_signal), -offset); reject; } diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 2680252a7..6ceb2b9b7 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -116,7 +116,7 @@ struct CutpointPass : public Pass { for (auto bit : sigmap(conn.second)) if (bit.wire) wire_drivers.insert(bit); - + for (auto wire : module->wires()) if (wire->port_input) for (auto bit : sigmap(wire)) diff --git a/passes/sat/qbfsat.h b/passes/sat/qbfsat.h index 3441b7819..ea5d44d7a 100644 --- a/passes/sat/qbfsat.h +++ b/passes/sat/qbfsat.h @@ -132,7 +132,7 @@ struct QbfSolutionType { //More importantly, we want to have the ability to port hole assignments to other modules with compatible //hole names and widths. Obviously in those cases source locations of the $anyconst cells will not match. // - //Option 2 has the benefits previously described, but wire names can be changed automatically by + //Option 2 has the benefits previously described, but wire names can be changed automatically by //optimization or techmapping passes, especially when (ex/im)porting from BLIF for optimization with ABC. // //The approach taken here is to allow both options. We write the assignment information for each bit of diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 2144b6266..bbddb2c16 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -155,7 +155,7 @@ void zinit(Const &v) struct SimInstance { SimShared *shared; - + std::string scope; Module *module; Cell *instance; @@ -183,7 +183,7 @@ struct SimInstance State past_clk; State past_ce; State past_srst; - + FfData data; }; @@ -1050,7 +1050,7 @@ struct SimInstance } } } - + for (auto signal : signal_database) { if (shared->hdlname && signal.first->name.isPublic() && signal.first->has_attribute(ID::hdlname)) { @@ -1182,7 +1182,7 @@ struct SimInstance { if (cell->is_mem_cell()) { std::string memid = cell->parameters.at(ID::MEMID).decode_string(); - for (auto &data : fst_memories[memid]) + for (auto &data : fst_memories[memid]) { std::string v = shared->fst->valueOf(data.second); set_memory_state(memid, Const(data.first), Const::from_string(v)); @@ -1399,7 +1399,7 @@ struct SimWorker : SimShared } for(auto& writer : outputfiles) writer->write(use_signal); - + if (writeback) { pool wbmods; top->writeback(wbmods); @@ -1592,7 +1592,7 @@ struct SimWorker : SimShared if (start_time.time < fst->getStartTime()) log_warning("Start time is before simulation file start time\n"); startCount = fst->getStartTime(); - } else if (start_time.end) + } else if (start_time.end) startCount = fst->getEndTime(); else { startCount = start_time.time * pow10(start_time.scale - fst->getScale()); @@ -1605,7 +1605,7 @@ struct SimWorker : SimShared if (stop_time.time < fst->getStartTime()) log_warning("Stop time is before simulation file start time\n"); stopCount = fst->getStartTime(); - } else if (stop_time.end) + } else if (stop_time.end) stopCount = fst->getEndTime(); else { stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale()); @@ -1621,7 +1621,7 @@ struct SimWorker : SimShared bool initial = true; int cycle = 0; log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString()); - if (cycles_set) + if (cycles_set) log(" for %d clock cycle(s)",numcycles); log("\n"); bool all_samples = fst_clock.empty(); @@ -1839,9 +1839,9 @@ struct SimWorker : SimShared std::getline(f, line); if (line.size()==0) continue; - if (line[0]=='#' || line[0]=='@' || line[0]=='.') { + if (line[0]=='#' || line[0]=='@' || line[0]=='.') { if (line[0]!='.') - curr_cycle = atoi(line.c_str()+1); + curr_cycle = atoi(line.c_str()+1); else curr_cycle = -1; // force detect change @@ -1907,7 +1907,7 @@ struct SimWorker : SimShared log_error("Cell %s not present in module %s\n",escaped_s.unescape(),topmod); if (!c->is_mem_cell()) log_error("Cell %s is not memory cell in module %s\n",escaped_s.unescape(),topmod); - + Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2)); Const data = Const::from_string(parts[2]); top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data); @@ -2252,7 +2252,7 @@ struct SimWorker : SimShared if (start_time.time < fst->getStartTime()) log_warning("Start time is before simulation file start time\n"); startCount = fst->getStartTime(); - } else if (start_time.end) + } else if (start_time.end) startCount = fst->getEndTime(); else { startCount = start_time.time * pow10(start_time.scale - fst->getScale()); @@ -2265,7 +2265,7 @@ struct SimWorker : SimShared if (stop_time.time < fst->getStartTime()) log_warning("Stop time is before simulation file start time\n"); stopCount = fst->getStartTime(); - } else if (stop_time.end) + } else if (stop_time.end) stopCount = fst->getEndTime(); else { stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale()); @@ -2280,7 +2280,7 @@ struct SimWorker : SimShared int cycle = 0; log("Generate testbench data from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString()); - if (cycles_set) + if (cycles_set) log(" for %d clock cycle(s)",numcycles); log("\n"); @@ -2351,22 +2351,22 @@ struct SimWorker : SimShared f << initstate.str(); f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename); - f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1); - f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1); + f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1); + f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1); f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1); f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle); - f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1); - f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1); + f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1); + f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1); f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1); - + f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1); f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n"; f << "\t\t\tend\n"; - + f << "\t\tend\n"; - + f << "\t\t$finish;\n"; f << "\tend\n"; f << "endmodule\n"; @@ -2483,7 +2483,7 @@ struct FSTWriter : public OutputWriter fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ); fstWriterSetRepackOnClose(fstfile, 1); - + worker->top->write_output_header( [this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); }, [this]() { fstWriterSetUpscope(fstfile); }, @@ -2632,7 +2632,7 @@ struct AIWWriter : public OutputWriter aiwfile << '0'; } aiwfile << '\n'; - } + } } std::ofstream aiwfile; @@ -3038,7 +3038,7 @@ struct Fst2TbPass : public Pass { log("\n"); log(" -n \n"); log(" number of clock cycles to simulate (default: 20)\n"); - log("\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index a54eef199..70748271e 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -159,7 +159,7 @@ void SynthPropWorker::run() if (tracing_data[module].names.size() == 0) return; if (!reset_name.empty()) { - int width = tracing_data[module].names.size(); + int width = tracing_data[module].names.size(); SigSpec reset = module->wire(reset_name); reset.extend_u0(width, true); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f7e2b53b5..164033a28 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -398,7 +398,7 @@ struct Abc9Pass : public ScriptPass log_error("Can't handle partially selected module %s!\n", mod); std::string tempdir_name; - if (cleanup) + if (cleanup) tempdir_name = get_base_tmpdir() + "/"; else tempdir_name = "_tmp_"; diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index 0a312fb77..91e17882f 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -135,7 +135,7 @@ struct AbcNewPass : public ScriptPass { void script() override { if (check_label("check")) { - run("abc9_ops -check"); + run("abc9_ops -check"); } if (check_label("prep_boxes")) { diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 972edc431..fb7084569 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -260,7 +260,7 @@ struct BoothPassWorker { y_sz_revised = y_sz + 1; } else { x_sz_revised = y_sz; - } + } } else { if (x_sz % 2 != 0) { y_sz_revised = x_sz + 1; @@ -804,7 +804,7 @@ struct BoothPassWorker { c_result = c_wire; debug_csa_trees[column_ix].push_back(csa); - csa_ix++; + csa_ix++; if (var_ix <= column_bits.size() - 1) carry_bits_to_sum.append(c_wire); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index d2755b53e..53f25c341 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -139,7 +139,7 @@ struct DffLegalizePass : public Pass { } // Table of all supported cell types. - // First index in the array is one of the FF_* values, second + // First index in the array is one of the FF_* values, second // index is the set of negative-polarity inputs (OR of NEG_* // values), and the value is the set of supported init values // (OR of INIT_* values). diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index c0e45a70e..02e3c82c6 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -326,12 +326,12 @@ int counter_tryextract( return 24; //Mux should have A driven by count Q, and B by muxy //if A and B are swapped, CE polarity is inverted - if(sigmap(cemux->getPort(ID::B)) == muxy && + if(sigmap(cemux->getPort(ID::B)) == muxy && sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q))) { extract.ce_inverted = false; } - else if(sigmap(cemux->getPort(ID::A)) == muxy && + else if(sigmap(cemux->getPort(ID::A)) == muxy && sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q))) { extract.ce_inverted = true; diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index facf4972f..fe3815cd1 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -652,7 +652,7 @@ LibertyAst *LibertyParser::parse(bool top_level) return NULL; if (tok != 'v') { - report_unexpected_token(tok); + report_unexpected_token(tok); } LibertyAst *ast = new LibertyAst; @@ -662,7 +662,7 @@ LibertyAst *LibertyParser::parse(bool top_level) { tok = lexer(str); - // allow both ';' and new lines to + // allow both ';' and new lines to // terminate a statement. if ((tok == ';') || (tok == 'n')) break; diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 2ddb16d61..e8ea2be05 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -33,7 +33,7 @@ int lut2mux(Cell *cell, bool word_mode) if (GetSize(sig_a) == 1) { if (!word_mode) - cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); else cell->module->addMux(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); } @@ -47,11 +47,11 @@ int lut2mux(Cell *cell, bool word_mode) Const lut1 = lut.extract(0, GetSize(lut)/2); Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); + count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2), word_mode); if (!word_mode) - cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); else cell->module->addMux(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 984926be8..1cc95f2c4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -333,7 +333,7 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - + if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) { c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype)); c->attributes.erase(ID::techmap_chtype); diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 2bf958d8f..e15c3f40d 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -958,7 +958,7 @@ module RAMD64X1 ( (DPRA2 => DPO) = 147; (DPRA3 => DPO) = 139; (DPRA4 => DPO) = 131; - (DPRA5 => DPO) = 64; + (DPRA5 => DPO) = 64; (posedge WCLK => (SPO : D)) = 761; (posedge WCLK => (DPO : D)) = 733; endspecify @@ -984,7 +984,7 @@ module RAMD64X1 ( (DPRA2 => DPO) = 513; (DPRA3 => DPO) = 505; (DPRA4 => DPO) = 496; - (DPRA5 => DPO) = 199; + (DPRA5 => DPO) = 199; (posedge WCLK => (SPO : D)) = 1798; (posedge WCLK => (DPO : D)) = 1807; endspecify diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index 5d09498f2..aec62a0dc 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -48,8 +48,8 @@ static void fix_carry_chain(Module *module) SigSpec o = cell->getPort(ID(o)); if (GetSize(o) == 2) { SigBit bit_o = o[0]; - ci_bits.insert(bit_ci); - mapping_bits[bit_ci] = bit_o; + ci_bits.insert(bit_ci); + mapping_bits[bit_ci] = bit_o; } } } @@ -64,8 +64,8 @@ static void fix_carry_chain(Module *module) SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b))); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) - continue; - if (bit_i0 == State::S0 && bit_i1== State::S0) + continue; + if (bit_i0 == State::S0 && bit_i1== State::S0) continue; adders_to_fix_cells.push_back(cell); @@ -90,10 +90,10 @@ static void fix_carry_chain(Module *module) c->setPort(ID(b), State::S0); c->setPort(ID(c), State::S0); c->setPort(ID(o), bits); - + cell->setPort(ID(c), new_bit); } - + } struct AnlogicCarryFixPass : public Pass { @@ -110,7 +110,7 @@ struct AnlogicCarryFixPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n"); - + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -123,7 +123,7 @@ struct AnlogicCarryFixPass : public Pass { if (module == nullptr) log_cmd_error("No top module found.\n"); - fix_carry_chain(module); + fix_carry_chain(module); } } AnlogicCarryFixPass; diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index f0cec4909..13d89d003 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -36,7 +36,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); input CI, BI; (* force_downto *) output [Y_WIDTH-1:0] CO; - + wire CIx; (* force_downto *) wire [Y_WIDTH-1:0] COx; @@ -85,7 +85,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); .c(COx[i]), .o({cout, CO[i]}) ); - end: slice + end: slice endgenerate /* End implementation */ diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index e8ecf4f03..dfddc385a 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -82,7 +82,7 @@ module AL_MAP_LUT1 ( parameter [1:0] INIT = 2'h0; parameter EQN = "(A)"; - assign o = a ? INIT[1] : INIT[0]; + assign o = a ? INIT[1] : INIT[0]; endmodule module AL_MAP_LUT2 ( @@ -94,7 +94,7 @@ module AL_MAP_LUT2 ( parameter EQN = "(A)"; wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0]; - assign o = a ? s1[1] : s1[0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT3 ( @@ -108,7 +108,7 @@ module AL_MAP_LUT3 ( wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0]; wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; - assign o = a ? s1[1] : s1[0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT4 ( @@ -124,7 +124,7 @@ module AL_MAP_LUT4 ( wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0]; wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0]; wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; - assign o = a ? s1[1] : s1[0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT5 ( @@ -186,6 +186,6 @@ module AL_MAP_ADDER ( "A_LE_B_CARRY": assign o = { a, 1'b0 }; default: assign o = a + b + c; endcase - endgenerate + endgenerate endmodule diff --git a/techlibs/anlogic/eagle_bb.v b/techlibs/anlogic/eagle_bb.v index 7cbec331a..5ad4c7a7c 100644 --- a/techlibs/anlogic/eagle_bb.v +++ b/techlibs/anlogic/eagle_bb.v @@ -44,7 +44,7 @@ endmodule (* blackbox *) module EG_LOGIC_MBOOT( input rebootn, - input [7:0] dynamic_addr + input [7:0] dynamic_addr ); parameter ADDR_SOURCE_SEL = "STATIC"; parameter STATIC_ADDR = 8'b00000000; @@ -242,7 +242,7 @@ module EG_LOGIC_MULT( input rstan, input rstbn, input rstpdn -); +); parameter INPUT_WIDTH_A = 18; parameter INPUT_WIDTH_B = 18; parameter OUTPUT_WIDTH = 36; @@ -561,7 +561,7 @@ module EG_PHY_FIFO( parameter [13:0] F = 14'b01111111110000; parameter [13:0] AEP1 = 14'b00000001110000; parameter [13:0] AFM1 = 14'b01111110000000; - parameter [13:0] FM1 = 14'b01111111100000; + parameter [13:0] FM1 = 14'b01111111100000; parameter [4:0] E = 5'b00000; parameter [5:0] EP1 = 6'b010000; parameter GSR = "ENABLE"; @@ -604,8 +604,8 @@ module EG_PHY_MULT18( input rstbn, input rstpdn, input sourcea, - input sourceb -); + input sourceb +); parameter INPUTREGA = "ENABLE"; parameter INPUTREGB = "ENABLE"; parameter OUTPUTREG = "ENABLE"; @@ -628,7 +628,7 @@ endmodule module EG_PHY_GCLK( input clki, output clko -); +); endmodule (* blackbox *) @@ -647,7 +647,7 @@ module EG_PHY_CLKDIV( input clki, input rst, input rls -); +); parameter GSR = "DISABLE"; parameter DIV = 2; endmodule @@ -677,7 +677,7 @@ module EG_PHY_CONFIG( input dna_shift_en, input mboot_rebootn, input [7:0] mboot_dynamic_addr -); +); parameter MBOOT_AUTO_SEL = "DISABLE"; parameter ADDR_SOURCE_SEL = "STATIC"; parameter STATIC_ADDR = 8'b0; @@ -694,7 +694,7 @@ endmodule module EG_PHY_OSC( input osc_dis, output osc_clk -); +); parameter STDBY = "DISABLE"; endmodule @@ -919,7 +919,7 @@ module EG_PHY_PLL( parameter CLKC3_DIV2_ENABLE = "DISABLE"; parameter CLKC4_DIV2_ENABLE = "DISABLE"; parameter FEEDBK_MODE = "NORMAL"; - parameter FEEDBK_PATH = "VCO_PHASE_0"; + parameter FEEDBK_PATH = "VCO_PHASE_0"; parameter STDBY_ENABLE = "ENABLE"; parameter CLKC0_FPHASE = 0; parameter CLKC1_FPHASE = 0; @@ -992,7 +992,7 @@ module EG_LOGIC_BRAM( parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B; parameter BYTE_ENABLE = 0; parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE; - parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE; + parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE; parameter MODE = "DP"; parameter REGMODE_A = "NOREG"; parameter REGMODE_B = "NOREG"; @@ -1005,7 +1005,7 @@ module EG_LOGIC_BRAM( parameter INIT_FILE = "NONE"; parameter FILL_ALL = "NONE"; parameter IMPLEMENT = "9K"; -endmodule +endmodule (* blackbox *) module EG_PHY_ADC( diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ca2b3c5cf..4ac03cad4 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -20,8 +20,8 @@ * --- * * Tech-mapping rules for decomposing arbitrarily-sized $mul cells - * into an equivalent collection of smaller `DSP_NAME cells (with the - * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached + * into an equivalent collection of smaller `DSP_NAME cells (with the + * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached * to $shl and $add cells. * */ diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 3f34bfd22..2f3998f68 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -476,7 +476,7 @@ endmodule //- $sshl (A, B, Y) //* group binary //- -//- An arithmatic shift-left operation. +//- An arithmatic shift-left operation. //- This corresponds to the Verilog '<<<' operator. //- module \$sshl (A, B, Y); @@ -720,7 +720,7 @@ endmodule //- $lt (A, B, Y) //* group binary //- -//- A less-than comparison between inputs 'A' and 'B'. +//- A less-than comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '<' operator. //- module \$lt (A, B, Y); @@ -752,7 +752,7 @@ endmodule //- $le (A, B, Y) //* group binary //- -//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. +//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '<=' operator. //- module \$le (A, B, Y); @@ -784,7 +784,7 @@ endmodule //- $eq (A, B, Y) //* group binary //- -//- An equality comparison between inputs 'A' and 'B'. +//- An equality comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '==' operator. //- module \$eq (A, B, Y); @@ -816,7 +816,7 @@ endmodule //- $ne (A, B, Y) //* group binary //- -//- An inequality comparison between inputs 'A' and 'B'. +//- An inequality comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '!=' operator. //- module \$ne (A, B, Y); @@ -944,7 +944,7 @@ endmodule //- $gt (A, B, Y) //* group binary //- -//- A greater-than comparison between inputs 'A' and 'B'. +//- A greater-than comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '>' operator. //- module \$gt (A, B, Y); @@ -1477,7 +1477,7 @@ endmodule //- $pow (A, B, Y) //* group binary //- -//- Exponentiation of an input (Y = A ** B). +//- Exponentiation of an input (Y = A ** B). //- This corresponds to the Verilog '**' operator. //- `ifndef SIMLIB_NOPOW @@ -1809,7 +1809,7 @@ endmodule //- //- $tribuf (A, EN, Y) //- -//- A tri-state buffer. +//- A tri-state buffer. //- This buffer conditionally drives the output with the value of the input //- based on the enable signal. //- diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index 6bda0505c..551950980 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -36,7 +36,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); input CI, BI; (* force_downto *) output [Y_WIDTH-1:0] CO; - + wire CIx; (* force_downto *) wire [Y_WIDTH-1:0] COx; @@ -73,14 +73,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); .O(Y[i]), .CO(COx[i]) ); - EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) adder_cout ( .I0(1'b0), .I1(1'b0), .CI(COx[i]), .O(CO[i]) ); - end: slice + end: slice endgenerate /* End implementation */ diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v index 752010f45..23e4420f3 100644 --- a/techlibs/efinix/brams_map.v +++ b/techlibs/efinix/brams_map.v @@ -33,14 +33,14 @@ module $__EFINIX_5K_ (...); PORT_W_WIDTH == 10 ? 9 : 8; - localparam READ_WIDTH = + localparam READ_WIDTH = PORT_R_WIDTH == 1 ? 1 : PORT_R_WIDTH == 2 ? 2 : PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) : PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) : (IS_5BIT ? 20 : 16); - localparam WRITE_WIDTH = + localparam WRITE_WIDTH = PORT_W_WIDTH == 1 ? 1 : PORT_W_WIDTH == 2 ? 2 : PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) : diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v index 26e454646..dce4397b1 100644 --- a/techlibs/efinix/cells_sim.v +++ b/techlibs/efinix/cells_sim.v @@ -1,5 +1,5 @@ module EFX_LUT4( - output O, + output O, input I0, input I1, input I2, @@ -10,7 +10,7 @@ module EFX_LUT4( wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0]; wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0]; wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; + assign O = I0 ? s1[1] : s1[0]; endmodule module EFX_ADD( @@ -64,9 +64,9 @@ module EFX_FF( initial Q = 1'b0; generate - if (SR_SYNC == 1) + if (SR_SYNC == 1) begin - if (SR_SYNC_PRIORITY == 1) + if (SR_SYNC_PRIORITY == 1) begin always @(posedge clk) if (sr) @@ -93,7 +93,7 @@ module EFX_FF( Q <= SR_VALUE; else if (ce) Q <= d; - + end endgenerate endmodule @@ -108,16 +108,16 @@ module EFX_GBUFCE( wire ce; assign ce = CE_POLARITY ? CE : ~CE; - + assign O = I & ce; - + endmodule module EFX_RAM_5K # ( parameter READ_WIDTH = 20, parameter WRITE_WIDTH = 20, - localparam READ_ADDR_WIDTH = + localparam READ_ADDR_WIDTH = (READ_WIDTH == 16) ? 8 : // 256x16 (READ_WIDTH == 8) ? 9 : // 512x8 (READ_WIDTH == 4) ? 10 : // 1024x4 @@ -126,8 +126,8 @@ module EFX_RAM_5K (READ_WIDTH == 20) ? 8 : // 256x20 (READ_WIDTH == 10) ? 9 : // 512x10 (READ_WIDTH == 5) ? 10 : -1, // 1024x5 - - localparam WRITE_ADDR_WIDTH = + + localparam WRITE_ADDR_WIDTH = (WRITE_WIDTH == 16) ? 8 : // 256x16 (WRITE_WIDTH == 8) ? 9 : // 512x8 (WRITE_WIDTH == 4) ? 10 : // 1024x4 @@ -140,13 +140,13 @@ module EFX_RAM_5K ( input [WRITE_WIDTH-1:0] WDATA, input [WRITE_ADDR_WIDTH-1:0] WADDR, - input WE, + input WE, (* clkbuf_sink *) input WCLK, - input WCLKE, - output [READ_WIDTH-1:0] RDATA, + input WCLKE, + output [READ_WIDTH-1:0] RDATA, input [READ_ADDR_WIDTH-1:0] RADDR, - input RE, + input RE, (* clkbuf_sink *) input RCLK ); diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index 5056dec1a..47432d72c 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -45,12 +45,12 @@ static void fix_carry_chain(Module *module) if (bit_i0 == State::S0 && bit_i1== State::S0) { SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); SigBit bit_o = sigmap(cell->getPort(ID::O)); - ci_bits.insert(bit_ci); + ci_bits.insert(bit_ci); mapping_bits[bit_ci] = bit_o; } } } - + vector adders_to_fix_cells; for (auto cell : module->cells()) { @@ -60,8 +60,8 @@ static void fix_carry_chain(Module *module) SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) - continue; - if (bit_i0 == State::S0 && bit_i1== State::S0) + continue; + if (bit_i0 == State::S0 && bit_i1== State::S0) continue; adders_to_fix_cells.push_back(cell); @@ -83,7 +83,7 @@ static void fix_carry_chain(Module *module) c->setPort(ID(I1), State::S1); c->setPort(ID::CI, State::S0); c->setPort(ID::CO, new_bit); - + cell->setPort(ID::CI, new_bit); } } @@ -102,7 +102,7 @@ struct EfinixCarryFixPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n"); - + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -115,7 +115,7 @@ struct EfinixCarryFixPass : public Pass { if (module == nullptr) log_cmd_error("No top module found.\n"); - fix_carry_chain(module); + fix_carry_chain(module); } } EfinixCarryFixPass; diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v index 0dab9b8fd..d1c493080 100644 --- a/techlibs/fabulous/prims.v +++ b/techlibs/fabulous/prims.v @@ -108,7 +108,7 @@ module FABULOUS_LC #( output Q ); wire f_wire; - + //LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); generate if (K == 1) begin @@ -124,7 +124,7 @@ module FABULOUS_LC #( LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3])); end endgenerate - + LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); assign O = f_wire; @@ -255,15 +255,15 @@ module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label - wire [7:0] A; // port A read data - wire [7:0] B; // port B read data - wire [19:0] C; // port B read data + wire [7:0] A; // port A read data + wire [7:0] B; // port B read data + wire [19:0] C; // port B read data reg [7:0] A_q; // port A read data register reg [7:0] B_q; // port B read data register reg [19:0] C_q; // port B read data register - wire [7:0] OPA; // port A - wire [7:0] OPB; // port B - wire [19:0] OPC; // port B + wire [7:0] OPA; // port A + wire [7:0] OPB; // port B + wire [19:0] OPC; // port B reg [19:0] ACC_data ; // accumulator register wire [19:0] sum;// port B read data register wire [19:0] sum_in;// port B read data register @@ -337,7 +337,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e input W_ADR3; input W_ADR4; input W_en; - + output AD0;// Register File read port A output AD1; output AD2; @@ -359,9 +359,9 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e input B_ADR4; input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) - + // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label - + //type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit //signal mem : memtype := (others => (others => '0')); @@ -377,7 +377,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e reg [3:0] AD_q; // port A read data register reg [3:0] BD_q; // port B read data register - + integer i; assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0}; @@ -385,7 +385,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0}; assign D = {D3,D2,D1,D0}; - + initial begin for (i=0; i<32; i=i+1) begin mem[i] = 4'b0000; diff --git a/techlibs/fix_mod.py b/techlibs/fix_mod.py index d6406108d..647bb0dfb 100644 --- a/techlibs/fix_mod.py +++ b/techlibs/fix_mod.py @@ -23,7 +23,7 @@ def main(): in_mod = True elif in_mod: decl += line - + if in_mod and decl.rstrip()[-1] == ';': in_mod = False modules[mod] = decl diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index a69f27619..aa1764639 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -211,7 +211,7 @@ struct GatemateFoldInvPass : public Pass { for (Module *module : design->selected_modules()) { FoldInvWorker worker(module); worker(); - } + } } } GatemateFoldInvPass; diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 716c212d2..ff94e4c84 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -25,7 +25,7 @@ module LUT3(output F, input I0, I1, I2); (I0 => F) = (1054, 1486); (I1 => F) = (867, 1184); (I2 => F) = (555, 902); - endspecify + endspecify wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign F = I0 ? s1[1] : s1[0]; @@ -39,7 +39,7 @@ module LUT4(output F, input I0, I1, I2, I3); (I1 => F) = (1053, 1583); (I2 => F) = (867, 1184); (I3 => F) = (555, 902); - endspecify + endspecify wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; @@ -54,7 +54,7 @@ module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0); (I2 => F) = (995, 1371); (I3 => F) = (808, 1116); (M0 => F) = (486, 680); - endspecify + endspecify endmodule (* abc9_lut=4 *) @@ -66,7 +66,7 @@ module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1); (I3 => F) = (808 + 136, 1116 + 255); (M0 => F) = (486 + 136, 680 + 255); (M1 => F) = (478, 723); - endspecify + endspecify endmodule (* abc9_lut=8 *) @@ -79,7 +79,7 @@ module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2); (M0 => F) = (486 + 136 + 136, 680 + 255 + 255); (M1 => F) = (478 + 136, 723 + 255); (M2 => F) = (478, 723); - endspecify + endspecify endmodule (* abc9_lut=16 *) @@ -93,7 +93,7 @@ module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3); (M1 => F) = (478 + 136 + 136, 723 + 255 + 255); (M2 => F) = (478 + 136, 723 + 255); (M3 => F) = (478, 723); - endspecify + endspecify endmodule module MUX2 (O, I0, I1, S0); @@ -212,7 +212,7 @@ module DFFS (output reg Q, input D, CLK, SET); if (SET) Q <= 1'b1; else - Q <= D; + Q <= D; end endmodule // DFFS (positive clock edge; synchronous set) @@ -388,7 +388,7 @@ endmodule // DFFNE (negative clock edge; clock enable) module DFFNS (output reg Q, input D, CLK, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; - + specify (negedge CLK => (Q : D)) = (480, 660); $setup(D, negedge CLK, 576); @@ -399,7 +399,7 @@ module DFFNS (output reg Q, input D, CLK, SET); if (SET) Q <= 1'b1; else - Q <= D; + Q <= D; end endmodule // DFFNS (negative clock edge; synchronous set) @@ -485,7 +485,7 @@ endmodule // DFFNP (negative clock edge; asynchronous preset) module DFFNPE (output reg Q, input D, CLK, CE, PRESET); parameter [0:0] INIT = 1'b1; initial Q = INIT; - + specify if (CE) (negedge CLK => (Q : D)) = (480, 660); (PRESET => Q) = (1800, 2679); @@ -793,7 +793,7 @@ module OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q); parameter LSREN = "true"; endmodule -module OSER16(D15, D14, D13, D12, D11, D10, +module OSER16(D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q); output Q; @@ -918,7 +918,7 @@ RESET, CALIB, D); parameter LSREN = "true"; endmodule -module IDES16(Q15, Q14, Q13, Q12, Q11, Q10, +module IDES16(Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK, RESET, CALIB, D); input D; diff --git a/techlibs/gowin/cells_xtra_gw1n.v b/techlibs/gowin/cells_xtra_gw1n.v index 0ab375ec8..2bf35eb40 100644 --- a/techlibs/gowin/cells_xtra_gw1n.v +++ b/techlibs/gowin/cells_xtra_gw1n.v @@ -36,7 +36,7 @@ endmodule module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); -parameter C_STATIC_DLY = 0; +parameter C_STATIC_DLY = 0; input DI; input SDTAP; input SETN; @@ -47,9 +47,9 @@ endmodule module IEM(D, CLK, RESET, MCLK, LAG, LEAD); -parameter WINSIZE = "SMALL"; -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter WINSIZE = "SMALL"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, CLK, RESET, MCLK; output LAG, LEAD; endmodule @@ -63,10 +63,10 @@ endmodule module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -132,9 +132,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [31:0] DO; @@ -142,11 +142,11 @@ endmodule module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -211,9 +211,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [35:0] DO; @@ -221,9 +221,9 @@ endmodule module pROM(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; -parameter RESET_MODE = "SYNC"; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -289,18 +289,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [31:0] DO; endmodule module pROMX9(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -365,20 +365,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [35:0] DO; endmodule module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 32; -parameter BIT_WIDTH_1 = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -444,8 +444,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [31:0] DI; input [2:0] BLKSELA, BLKSELB; @@ -454,13 +454,13 @@ endmodule module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 36; -parameter BIT_WIDTH_1 = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -525,8 +525,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [35:0] DI; @@ -535,15 +535,15 @@ endmodule module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 16; -parameter BIT_WIDTH_1 = 16; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -609,9 +609,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [15:0] DIA, DIB; @@ -620,16 +620,16 @@ endmodule module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 18; -parameter BIT_WIDTH_1 = 18; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -694,9 +694,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [17:0] DIA, DIB; input [2:0] BLKSELA, BLKSELB; @@ -712,11 +712,11 @@ input CE,CLK,RESET; input [17:0] SI,SBI; output [17:0] SO,SBO; output [17:0] DOUT; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -728,11 +728,11 @@ input CE,CLK,RESET; input [8:0] SI,SBI; output [8:0] SO,SBO; output [8:0] DOUT; -parameter AREG = 1'b0; -parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -752,8 +752,8 @@ parameter OUT_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); @@ -773,7 +773,7 @@ parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); @@ -791,7 +791,7 @@ parameter OUT1_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); @@ -814,9 +814,9 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; -parameter MULTALU36X18_MODE = 0; -parameter C_ADD_SUB = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter MULTALU36X18_MODE = 0; +parameter C_ADD_SUB = 1'b0; endmodule module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); @@ -836,7 +836,7 @@ input ACCLOAD; output [53:0] DOUT; output [54:0] CASO; output [17:0] SOA, SOB; -parameter A0REG = 1'b0; +parameter A0REG = 1'b0; parameter A1REG = 1'b0; parameter B0REG = 1'b0; parameter B1REG = 1'b0; @@ -851,7 +851,7 @@ parameter ACCLOAD_REG1 = 1'b0; parameter BSIGN0_REG = 1'b0; parameter BSIGN1_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; @@ -875,12 +875,12 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; parameter PIPE_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; -parameter MULTALU18X18_MODE = 0; +parameter MULTALU18X18_MODE = 0; endmodule module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); @@ -891,13 +891,13 @@ input [54:0] CASI; input CLK, CE, RESET; output [53:0] DOUT; output [54:0] CASO; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; @@ -918,41 +918,41 @@ endmodule module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3); input CLKIN; input CLKFB; -input RESET; -input RESET_P; +input RESET; +input RESET_P; input RESET_I; input RESET_S; -input [5:0] FBDSEL; +input [5:0] FBDSEL; input [5:0] IDSEL; input [5:0] ODSEL; -input [3:0] PSDA,FDLY; +input [3:0] PSDA,FDLY; input [3:0] DUTYDA; output CLKOUT; output LOCK; output CLKOUTP; output CLKOUTD; output CLKOUTD3; -parameter FCLKIN = "100.0"; +parameter FCLKIN = "100.0"; parameter DYN_IDIV_SEL= "false"; -parameter IDIV_SEL = 0; +parameter IDIV_SEL = 0; parameter DYN_FBDIV_SEL= "false"; -parameter FBDIV_SEL = 0; +parameter FBDIV_SEL = 0; parameter DYN_ODIV_SEL= "false"; -parameter ODIV_SEL = 8; +parameter ODIV_SEL = 8; parameter PSDA_SEL= "0000"; parameter DYN_DA_EN = "false"; parameter DUTYDA_SEL= "1000"; -parameter CLKOUT_FT_DIR = 1'b1; -parameter CLKOUTP_FT_DIR = 1'b1; -parameter CLKOUT_DLY_STEP = 0; -parameter CLKOUTP_DLY_STEP = 0; -parameter CLKFB_SEL = "internal"; -parameter CLKOUT_BYPASS = "false"; -parameter CLKOUTP_BYPASS = "false"; -parameter CLKOUTD_BYPASS = "false"; -parameter DYN_SDIV_SEL = 2; -parameter CLKOUTD_SRC = "CLKOUT"; -parameter CLKOUTD3_SRC = "CLKOUT"; +parameter CLKOUT_FT_DIR = 1'b1; +parameter CLKOUTP_FT_DIR = 1'b1; +parameter CLKOUT_DLY_STEP = 0; +parameter CLKOUTP_DLY_STEP = 0; +parameter CLKFB_SEL = "internal"; +parameter CLKOUT_BYPASS = "false"; +parameter CLKOUTP_BYPASS = "false"; +parameter CLKOUTD_BYPASS = "false"; +parameter DYN_SDIV_SEL = 2; +parameter CLKOUTD_SRC = "CLKOUT"; +parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW1N-4"; endmodule @@ -1034,8 +1034,8 @@ input HCLKIN; input RESETN; input CALIB; output CLKOUT; -parameter DIV_MODE = "2"; -parameter GSREN = "false"; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; endmodule module DHCEN(CLKIN, CE, CLKOUT); @@ -1049,9 +1049,9 @@ input [7:0] DLLSTEP; input DIR,LOADN,MOVE; output CLKOUT; output FLAG; -parameter DLL_INSEL = 1'b1; -parameter DLY_SIGN = 1'b0; -parameter DLY_ADJ = 0; +parameter DLL_INSEL = 1'b1; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; endmodule module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT); @@ -1084,7 +1084,7 @@ parameter IDLE = 4'd0, PRO_S4 = 4'd9, PRO_S5 = 4'd10, RD_S1 = 4'd11, - RD_S2 = 4'd12; + RD_S2 = 4'd12; endmodule module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); @@ -1113,7 +1113,7 @@ module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; - parameter DCS_MODE = "RISING"; + parameter DCS_MODE = "RISING"; endmodule module DQCE(CLKIN, CE, CLKOUT); @@ -1123,7 +1123,7 @@ output CLKOUT; endmodule module CLKDIV2(HCLKIN, RESETN, CLKOUT); -parameter GSREN = "false"; +parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule @@ -1153,7 +1153,7 @@ parameter IDLE = 4'd0, PRO_S4 = 4'd9, PRO_S5 = 4'd10, RD_S1 = 4'd11, - RD_S2 = 4'd12; + RD_S2 = 4'd12; endmodule module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); @@ -1175,5 +1175,5 @@ parameter IDLE = 4'd0, PRO_S4 = 4'd9, PRO_S5 = 4'd10, RD_S1 = 4'd11, - RD_S2 = 4'd12; + RD_S2 = 4'd12; endmodule diff --git a/techlibs/gowin/cells_xtra_gw2a.v b/techlibs/gowin/cells_xtra_gw2a.v index 643723db6..404a3e502 100644 --- a/techlibs/gowin/cells_xtra_gw2a.v +++ b/techlibs/gowin/cells_xtra_gw2a.v @@ -36,8 +36,8 @@ endmodule module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, ICLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -47,10 +47,10 @@ endmodule module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter GSREN = "false"; +parameter LSREN = "true"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1; input TX, PCLK, TCLK, RESET; output Q0, Q1; @@ -58,8 +58,8 @@ endmodule module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3); -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -69,8 +69,8 @@ endmodule module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -80,11 +80,11 @@ endmodule module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter GSREN = "false"; +parameter LSREN = "true"; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3; input TX0, TX1; input PCLK, FCLK, TCLK, RESET; @@ -93,11 +93,11 @@ endmodule module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter GSREN = "false"; +parameter LSREN = "true"; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3, D4, D5, D6, D7; input TX0, TX1, TX2, TX3; input PCLK, FCLK, TCLK, RESET; @@ -106,7 +106,7 @@ endmodule module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); -parameter C_STATIC_DLY = 0; +parameter C_STATIC_DLY = 0; input DI; input SDTAP; input SETN; @@ -117,9 +117,9 @@ endmodule module IEM(D, CLK, RESET, MCLK, LAG, LEAD); -parameter WINSIZE = "SMALL"; -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter WINSIZE = "SMALL"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, CLK, RESET, MCLK; output LAG, LEAD; endmodule @@ -133,10 +133,10 @@ endmodule module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -202,9 +202,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [31:0] DO; @@ -212,11 +212,11 @@ endmodule module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -281,9 +281,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [35:0] DO; @@ -291,9 +291,9 @@ endmodule module pROM(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; -parameter RESET_MODE = "SYNC"; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -359,18 +359,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [31:0] DO; endmodule module pROMX9(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -435,20 +435,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [35:0] DO; endmodule module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 32; -parameter BIT_WIDTH_1 = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -514,8 +514,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [31:0] DI; input [2:0] BLKSELA, BLKSELB; @@ -524,13 +524,13 @@ endmodule module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 36; -parameter BIT_WIDTH_1 = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -595,8 +595,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [35:0] DI; @@ -605,15 +605,15 @@ endmodule module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 16; -parameter BIT_WIDTH_1 = 16; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -679,9 +679,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [15:0] DIA, DIB; @@ -690,16 +690,16 @@ endmodule module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 18; -parameter BIT_WIDTH_1 = 18; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -764,9 +764,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [17:0] DIA, DIB; input [2:0] BLKSELA, BLKSELB; @@ -782,11 +782,11 @@ input CE,CLK,RESET; input [17:0] SI,SBI; output [17:0] SO,SBO; output [17:0] DOUT; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -798,11 +798,11 @@ input CE,CLK,RESET; input [8:0] SI,SBI; output [8:0] SO,SBO; output [8:0] DOUT; -parameter AREG = 1'b0; -parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -822,8 +822,8 @@ parameter OUT_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); @@ -843,7 +843,7 @@ parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); @@ -861,7 +861,7 @@ parameter OUT1_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); @@ -884,9 +884,9 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; -parameter MULTALU36X18_MODE = 0; -parameter C_ADD_SUB = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter MULTALU36X18_MODE = 0; +parameter C_ADD_SUB = 1'b0; endmodule module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); @@ -906,7 +906,7 @@ input ACCLOAD; output [53:0] DOUT; output [54:0] CASO; output [17:0] SOA, SOB; -parameter A0REG = 1'b0; +parameter A0REG = 1'b0; parameter A1REG = 1'b0; parameter B0REG = 1'b0; parameter B1REG = 1'b0; @@ -921,7 +921,7 @@ parameter ACCLOAD_REG1 = 1'b0; parameter BSIGN0_REG = 1'b0; parameter BSIGN1_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; @@ -945,12 +945,12 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; parameter PIPE_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; -parameter MULTALU18X18_MODE = 0; +parameter MULTALU18X18_MODE = 0; endmodule module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); @@ -961,13 +961,13 @@ input [54:0] CASI; input CLK, CE, RESET; output [53:0] DOUT; output [54:0] CASO; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; @@ -1002,27 +1002,27 @@ output LOCK; output CLKOUTP; output CLKOUTD; output CLKOUTD3; -parameter FCLKIN = "100.0"; +parameter FCLKIN = "100.0"; parameter DYN_IDIV_SEL= "false"; -parameter IDIV_SEL = 0; +parameter IDIV_SEL = 0; parameter DYN_FBDIV_SEL= "false"; -parameter FBDIV_SEL = 0; +parameter FBDIV_SEL = 0; parameter DYN_ODIV_SEL= "false"; -parameter ODIV_SEL = 8; +parameter ODIV_SEL = 8; parameter PSDA_SEL= "0000"; parameter DYN_DA_EN = "false"; parameter DUTYDA_SEL= "1000"; -parameter CLKOUT_FT_DIR = 1'b1; -parameter CLKOUTP_FT_DIR = 1'b1; -parameter CLKOUT_DLY_STEP = 0; -parameter CLKOUTP_DLY_STEP = 0; -parameter CLKFB_SEL = "internal"; -parameter CLKOUT_BYPASS = "false"; -parameter CLKOUTP_BYPASS = "false"; -parameter CLKOUTD_BYPASS = "false"; -parameter DYN_SDIV_SEL = 2; -parameter CLKOUTD_SRC = "CLKOUT"; -parameter CLKOUTD3_SRC = "CLKOUT"; +parameter CLKOUT_FT_DIR = 1'b1; +parameter CLKOUTP_FT_DIR = 1'b1; +parameter CLKOUT_DLY_STEP = 0; +parameter CLKOUTP_DLY_STEP = 0; +parameter CLKFB_SEL = "internal"; +parameter CLKOUT_BYPASS = "false"; +parameter CLKOUTP_BYPASS = "false"; +parameter CLKOUTD_BYPASS = "false"; +parameter DYN_SDIV_SEL = 2; +parameter CLKOUTD_SRC = "CLKOUT"; +parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW2A-18"; endmodule @@ -1063,8 +1063,8 @@ input HCLKIN; input RESETN; input CALIB; output CLKOUT; -parameter DIV_MODE = "2"; -parameter GSREN = "false"; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; endmodule module DHCEN(CLKIN, CE, CLKOUT); @@ -1080,14 +1080,14 @@ input [2:0] RCLKSEL; input [7:0] DLLSTEP; input [7:0] WSTEP; input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD; -output DQSR90, DQSW0, DQSW270; +output DQSR90, DQSW0, DQSW270; output [2:0] RPOINT, WPOINT; output RVALID,RBURST, RFLAG, WFLAG; - parameter FIFO_MODE_SEL = 1'b0; - parameter RD_PNTR = 3'b000; - parameter DQS_MODE = "X1"; - parameter HWL = "false"; - parameter GSREN = "false"; + parameter FIFO_MODE_SEL = 1'b0; + parameter RD_PNTR = 3'b000; + parameter DQS_MODE = "X1"; + parameter HWL = "false"; + parameter GSREN = "false"; endmodule module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG); @@ -1096,16 +1096,16 @@ input [7:0] DLLSTEP; input DIR,LOADN,MOVE; output CLKOUT; output FLAG; -parameter DLL_INSEL = 1'b1; -parameter DLY_SIGN = 1'b0; -parameter DLY_ADJ = 0; +parameter DLL_INSEL = 1'b1; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; endmodule module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; - parameter DCS_MODE = "RISING"; + parameter DCS_MODE = "RISING"; endmodule module DQCE(CLKIN, CE, CLKOUT); @@ -1115,7 +1115,7 @@ output CLKOUT; endmodule module CLKDIV2(HCLKIN, RESETN, CLKOUT); -parameter GSREN = "false"; +parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v index ba85e928f..a06c4f936 100644 --- a/techlibs/gowin/cells_xtra_gw5a.v +++ b/techlibs/gowin/cells_xtra_gw5a.v @@ -120,12 +120,12 @@ input OEN, OENB, MODESEL, VCOME; endmodule module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, BLKSELA, BLKSELB, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 32; -parameter BIT_WIDTH_1 = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -191,8 +191,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] ADA, ADB; input [31:0] DI; input [2:0] BLKSELA, BLKSELB; @@ -201,13 +201,13 @@ endmodule module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, BLKSELA, BLKSELB, DI, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 36; -parameter BIT_WIDTH_1 = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -272,8 +272,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [35:0] DI; @@ -282,15 +282,15 @@ endmodule module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 16; -parameter BIT_WIDTH_1 = 16; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -356,9 +356,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [15:0] DIA, DIB; @@ -367,16 +367,16 @@ endmodule module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 18; -parameter BIT_WIDTH_1 = 18; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -441,9 +441,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [17:0] DIA, DIB; input [2:0] BLKSELA, BLKSELB; @@ -452,9 +452,9 @@ endmodule module pROM(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; -parameter RESET_MODE = "SYNC"; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -520,18 +520,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [31:0] DO; endmodule module pROMX9(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -596,21 +596,21 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [35:0] DO; endmodule module SDP36KE(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, DIP, BLKSELA, BLKSELB, DECCI, SECCI, DO, DOP, DECCO, SECCO, ECCP); -parameter ECC_WRITE_EN="TRUE"; -parameter ECC_READ_EN="TRUE"; -parameter READ_MODE = 1'b0; +parameter ECC_WRITE_EN="TRUE"; +parameter ECC_READ_EN="TRUE"; +parameter READ_MODE = 1'b0; parameter BLK_SEL_A = 3'b000; parameter BLK_SEL_B = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_FILE = "NONE"; +parameter RESET_MODE = "SYNC"; +parameter INIT_FILE = "NONE"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -756,8 +756,8 @@ parameter INITP_RAM_0D = 256'h00000000000000000000000000000000000000000000000000 parameter INITP_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESET; +input OCE; +input RESET; input [8:0] ADA, ADB; input [63:0] DI; input [7:0] DIP; @@ -779,52 +779,52 @@ output [67:0] DO; endmodule module MULTADDALU12X12(DOUT, CASO, A0, B0, A1, B1, CASI, ACCSEL, CASISEL, ADDSUB, CLK, CE, RESET); -parameter A0REG_CLK = "BYPASS"; -parameter A0REG_CE = "CE0"; -parameter A0REG_RESET = "RESET0"; -parameter A1REG_CLK = "BYPASS"; -parameter A1REG_CE = "CE0"; -parameter A1REG_RESET = "RESET0"; -parameter B0REG_CLK = "BYPASS"; -parameter B0REG_CE = "CE0"; -parameter B0REG_RESET = "RESET0"; -parameter B1REG_CLK = "BYPASS"; -parameter B1REG_CE = "CE0"; -parameter B1REG_RESET = "RESET0"; -parameter ACCSEL_IREG_CLK = "BYPASS"; -parameter ACCSEL_IREG_CE = "CE0"; -parameter ACCSEL_IREG_RESET = "RESET0"; -parameter CASISEL_IREG_CLK = "BYPASS"; -parameter CASISEL_IREG_CE = "CE0"; -parameter CASISEL_IREG_RESET = "RESET0"; -parameter ADDSUB0_IREG_CLK = "BYPASS"; -parameter ADDSUB0_IREG_CE = "CE0"; -parameter ADDSUB0_IREG_RESET = "RESET0"; -parameter ADDSUB1_IREG_CLK = "BYPASS"; -parameter ADDSUB1_IREG_CE = "CE0"; -parameter ADDSUB1_IREG_RESET = "RESET0"; -parameter PREG0_CLK = "BYPASS"; -parameter PREG0_CE = "CE0"; -parameter PREG0_RESET = "RESET0"; -parameter PREG1_CLK = "BYPASS"; -parameter PREG1_CE = "CE0"; -parameter PREG1_RESET = "RESET0"; -parameter FB_PREG_EN = "FALSE"; -parameter ACCSEL_PREG_CLK = "BYPASS"; -parameter ACCSEL_PREG_CE = "CE0"; -parameter ACCSEL_PREG_RESET = "RESET0"; -parameter CASISEL_PREG_CLK = "BYPASS"; -parameter CASISEL_PREG_CE = "CE0"; -parameter CASISEL_PREG_RESET = "RESET0"; -parameter ADDSUB0_PREG_CLK = "BYPASS"; -parameter ADDSUB0_PREG_CE = "CE0"; -parameter ADDSUB0_PREG_RESET = "RESET0"; -parameter ADDSUB1_PREG_CLK = "BYPASS"; -parameter ADDSUB1_PREG_CE = "CE0"; -parameter ADDSUB1_PREG_RESET = "RESET0"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter A0REG_CLK = "BYPASS"; +parameter A0REG_CE = "CE0"; +parameter A0REG_RESET = "RESET0"; +parameter A1REG_CLK = "BYPASS"; +parameter A1REG_CE = "CE0"; +parameter A1REG_RESET = "RESET0"; +parameter B0REG_CLK = "BYPASS"; +parameter B0REG_CE = "CE0"; +parameter B0REG_RESET = "RESET0"; +parameter B1REG_CLK = "BYPASS"; +parameter B1REG_CE = "CE0"; +parameter B1REG_RESET = "RESET0"; +parameter ACCSEL_IREG_CLK = "BYPASS"; +parameter ACCSEL_IREG_CE = "CE0"; +parameter ACCSEL_IREG_RESET = "RESET0"; +parameter CASISEL_IREG_CLK = "BYPASS"; +parameter CASISEL_IREG_CE = "CE0"; +parameter CASISEL_IREG_RESET = "RESET0"; +parameter ADDSUB0_IREG_CLK = "BYPASS"; +parameter ADDSUB0_IREG_CE = "CE0"; +parameter ADDSUB0_IREG_RESET = "RESET0"; +parameter ADDSUB1_IREG_CLK = "BYPASS"; +parameter ADDSUB1_IREG_CE = "CE0"; +parameter ADDSUB1_IREG_RESET = "RESET0"; +parameter PREG0_CLK = "BYPASS"; +parameter PREG0_CE = "CE0"; +parameter PREG0_RESET = "RESET0"; +parameter PREG1_CLK = "BYPASS"; +parameter PREG1_CE = "CE0"; +parameter PREG1_RESET = "RESET0"; +parameter FB_PREG_EN = "FALSE"; +parameter ACCSEL_PREG_CLK = "BYPASS"; +parameter ACCSEL_PREG_CE = "CE0"; +parameter ACCSEL_PREG_RESET = "RESET0"; +parameter CASISEL_PREG_CLK = "BYPASS"; +parameter CASISEL_PREG_CE = "CE0"; +parameter CASISEL_PREG_RESET = "RESET0"; +parameter ADDSUB0_PREG_CLK = "BYPASS"; +parameter ADDSUB0_PREG_CE = "CE0"; +parameter ADDSUB0_PREG_RESET = "RESET0"; +parameter ADDSUB1_PREG_CLK = "BYPASS"; +parameter ADDSUB1_PREG_CE = "CE0"; +parameter ADDSUB1_PREG_RESET = "RESET0"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; parameter PRE_LOAD = 48'h000000000000; parameter DYN_ADD_SUB_0 = "FALSE"; @@ -845,65 +845,65 @@ input [1:0] CLK, CE, RESET; endmodule module MULTALU27X18(DOUT, CASO, SOA, A, SIA, B, C, D, CASI, ACCSEL, PSEL, ASEL, PADDSUB, CSEL, CASISEL, ADDSUB, CLK, CE, RESET); -parameter AREG_CLK = "BYPASS"; -parameter AREG_CE = "CE0"; -parameter AREG_RESET = "RESET0"; -parameter BREG_CLK = "BYPASS"; -parameter BREG_CE = "CE0"; -parameter BREG_RESET = "RESET0"; -parameter DREG_CLK = "BYPASS"; -parameter DREG_CE = "CE0"; -parameter DREG_RESET = "RESET0"; -parameter C_IREG_CLK = "BYPASS"; -parameter C_IREG_CE = "CE0"; -parameter C_IREG_RESET = "RESET0"; -parameter PSEL_IREG_CLK = "BYPASS"; -parameter PSEL_IREG_CE = "CE0"; -parameter PSEL_IREG_RESET = "RESET0"; -parameter PADDSUB_IREG_CLK = "BYPASS"; -parameter PADDSUB_IREG_CE = "CE0"; -parameter PADDSUB_IREG_RESET = "RESET0"; -parameter ADDSUB0_IREG_CLK = "BYPASS"; -parameter ADDSUB0_IREG_CE = "CE0"; -parameter ADDSUB0_IREG_RESET = "RESET0"; -parameter ADDSUB1_IREG_CLK = "BYPASS"; -parameter ADDSUB1_IREG_CE = "CE0"; -parameter ADDSUB1_IREG_RESET = "RESET0"; -parameter CSEL_IREG_CLK = "BYPASS"; -parameter CSEL_IREG_CE = "CE0"; -parameter CSEL_IREG_RESET = "RESET0"; -parameter CASISEL_IREG_CLK = "BYPASS"; -parameter CASISEL_IREG_CE = "CE0"; -parameter CASISEL_IREG_RESET = "RESET0"; -parameter ACCSEL_IREG_CLK = "BYPASS"; -parameter ACCSEL_IREG_CE = "CE0"; -parameter ACCSEL_IREG_RESET = "RESET0"; -parameter PREG_CLK = "BYPASS"; -parameter PREG_CE = "CE0"; -parameter PREG_RESET = "RESET0"; -parameter ADDSUB0_PREG_CLK = "BYPASS"; -parameter ADDSUB0_PREG_CE = "CE0"; -parameter ADDSUB0_PREG_RESET = "RESET0"; -parameter ADDSUB1_PREG_CLK = "BYPASS"; -parameter ADDSUB1_PREG_CE = "CE0"; -parameter ADDSUB1_PREG_RESET = "RESET0"; -parameter CSEL_PREG_CLK = "BYPASS"; -parameter CSEL_PREG_CE = "CE0"; -parameter CSEL_PREG_RESET = "RESET0"; -parameter CASISEL_PREG_CLK = "BYPASS"; -parameter CASISEL_PREG_CE = "CE0"; -parameter CASISEL_PREG_RESET = "RESET0"; -parameter ACCSEL_PREG_CLK = "BYPASS"; -parameter ACCSEL_PREG_CE = "CE0"; -parameter ACCSEL_PREG_RESET = "RESET0"; -parameter C_PREG_CLK = "BYPASS"; -parameter C_PREG_CE = "CE0"; -parameter C_PREG_RESET = "RESET0"; -parameter FB_PREG_EN = "FALSE"; -parameter SOA_PREG_EN = "FALSE"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter AREG_CLK = "BYPASS"; +parameter AREG_CE = "CE0"; +parameter AREG_RESET = "RESET0"; +parameter BREG_CLK = "BYPASS"; +parameter BREG_CE = "CE0"; +parameter BREG_RESET = "RESET0"; +parameter DREG_CLK = "BYPASS"; +parameter DREG_CE = "CE0"; +parameter DREG_RESET = "RESET0"; +parameter C_IREG_CLK = "BYPASS"; +parameter C_IREG_CE = "CE0"; +parameter C_IREG_RESET = "RESET0"; +parameter PSEL_IREG_CLK = "BYPASS"; +parameter PSEL_IREG_CE = "CE0"; +parameter PSEL_IREG_RESET = "RESET0"; +parameter PADDSUB_IREG_CLK = "BYPASS"; +parameter PADDSUB_IREG_CE = "CE0"; +parameter PADDSUB_IREG_RESET = "RESET0"; +parameter ADDSUB0_IREG_CLK = "BYPASS"; +parameter ADDSUB0_IREG_CE = "CE0"; +parameter ADDSUB0_IREG_RESET = "RESET0"; +parameter ADDSUB1_IREG_CLK = "BYPASS"; +parameter ADDSUB1_IREG_CE = "CE0"; +parameter ADDSUB1_IREG_RESET = "RESET0"; +parameter CSEL_IREG_CLK = "BYPASS"; +parameter CSEL_IREG_CE = "CE0"; +parameter CSEL_IREG_RESET = "RESET0"; +parameter CASISEL_IREG_CLK = "BYPASS"; +parameter CASISEL_IREG_CE = "CE0"; +parameter CASISEL_IREG_RESET = "RESET0"; +parameter ACCSEL_IREG_CLK = "BYPASS"; +parameter ACCSEL_IREG_CE = "CE0"; +parameter ACCSEL_IREG_RESET = "RESET0"; +parameter PREG_CLK = "BYPASS"; +parameter PREG_CE = "CE0"; +parameter PREG_RESET = "RESET0"; +parameter ADDSUB0_PREG_CLK = "BYPASS"; +parameter ADDSUB0_PREG_CE = "CE0"; +parameter ADDSUB0_PREG_RESET = "RESET0"; +parameter ADDSUB1_PREG_CLK = "BYPASS"; +parameter ADDSUB1_PREG_CE = "CE0"; +parameter ADDSUB1_PREG_RESET = "RESET0"; +parameter CSEL_PREG_CLK = "BYPASS"; +parameter CSEL_PREG_CE = "CE0"; +parameter CSEL_PREG_RESET = "RESET0"; +parameter CASISEL_PREG_CLK = "BYPASS"; +parameter CASISEL_PREG_CE = "CE0"; +parameter CASISEL_PREG_RESET = "RESET0"; +parameter ACCSEL_PREG_CLK = "BYPASS"; +parameter ACCSEL_PREG_CE = "CE0"; +parameter ACCSEL_PREG_RESET = "RESET0"; +parameter C_PREG_CLK = "BYPASS"; +parameter C_PREG_CE = "CE0"; +parameter C_PREG_RESET = "RESET0"; +parameter FB_PREG_EN = "FALSE"; +parameter SOA_PREG_EN = "FALSE"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; parameter PRE_LOAD = 48'h000000000000; parameter DYN_P_SEL = "FALSE"; @@ -940,18 +940,18 @@ input [1:0] CLK, CE, RESET; endmodule module MULT12X12(DOUT, A, B, CLK, CE, RESET); -parameter AREG_CLK = "BYPASS"; -parameter AREG_CE = "CE0"; -parameter AREG_RESET = "RESET0"; -parameter BREG_CLK = "BYPASS"; -parameter BREG_CE = "CE0"; -parameter BREG_RESET = "RESET0"; -parameter PREG_CLK = "BYPASS"; -parameter PREG_CE = "CE0"; -parameter PREG_RESET = "RESET0"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter AREG_CLK = "BYPASS"; +parameter AREG_CE = "CE0"; +parameter AREG_RESET = "RESET0"; +parameter BREG_CLK = "BYPASS"; +parameter BREG_CE = "CE0"; +parameter BREG_RESET = "RESET0"; +parameter PREG_CLK = "BYPASS"; +parameter PREG_CE = "CE0"; +parameter PREG_RESET = "RESET0"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; output [23:0] DOUT; input [11:0] A, B; @@ -959,27 +959,27 @@ input [1:0] CLK, CE, RESET; endmodule module MULT27X36(DOUT, A, B, D, CLK, CE, RESET, PSEL, PADDSUB); -parameter AREG_CLK = "BYPASS"; -parameter AREG_CE = "CE0"; -parameter AREG_RESET = "RESET0"; -parameter BREG_CLK = "BYPASS"; -parameter BREG_CE = "CE0"; -parameter BREG_RESET = "RESET0"; -parameter DREG_CLK = "BYPASS"; -parameter DREG_CE = "CE0"; -parameter DREG_RESET = "RESET0"; -parameter PADDSUB_IREG_CLK = "BYPASS"; -parameter PADDSUB_IREG_CE = "CE0"; -parameter PADDSUB_IREG_RESET = "RESET0"; -parameter PREG_CLK = "BYPASS"; -parameter PREG_CE = "CE0"; -parameter PREG_RESET = "RESET0"; -parameter PSEL_IREG_CLK = "BYPASS"; -parameter PSEL_IREG_CE = "CE0"; -parameter PSEL_IREG_RESET = "RESET0"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter AREG_CLK = "BYPASS"; +parameter AREG_CE = "CE0"; +parameter AREG_RESET = "RESET0"; +parameter BREG_CLK = "BYPASS"; +parameter BREG_CE = "CE0"; +parameter BREG_RESET = "RESET0"; +parameter DREG_CLK = "BYPASS"; +parameter DREG_CE = "CE0"; +parameter DREG_RESET = "RESET0"; +parameter PADDSUB_IREG_CLK = "BYPASS"; +parameter PADDSUB_IREG_CE = "CE0"; +parameter PADDSUB_IREG_RESET = "RESET0"; +parameter PREG_CLK = "BYPASS"; +parameter PREG_CE = "CE0"; +parameter PREG_RESET = "RESET0"; +parameter PSEL_IREG_CLK = "BYPASS"; +parameter PSEL_IREG_CE = "CE0"; +parameter PSEL_IREG_RESET = "RESET0"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; parameter DYN_P_SEL = "FALSE"; parameter P_SEL = 1'b0; @@ -1002,14 +1002,14 @@ input [9:0] DATAIN0, DATAIN1; input [9:0] DATAIN2; input RSTN; input [23:0] CASI; -parameter COFFIN_WIDTH = 4; -parameter DATAIN_WIDTH = 8; -parameter IREG = 1'b0; -parameter OREG = 1'b0; -parameter PREG = 1'b0; -parameter ACC_EN = "FALSE"; -parameter CASI_EN = "FALSE"; -parameter CASO_EN = "FALSE"; +parameter COFFIN_WIDTH = 4; +parameter DATAIN_WIDTH = 8; +parameter IREG = 1'b0; +parameter OREG = 1'b0; +parameter PREG = 1'b0; +parameter ACC_EN = "FALSE"; +parameter CASI_EN = "FALSE"; +parameter CASO_EN = "FALSE"; endmodule module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); @@ -1022,8 +1022,8 @@ endmodule module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1; input TX, PCLK, TCLK, RESET; output Q0, Q1; @@ -1060,9 +1060,9 @@ endmodule module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3; input TX0, TX1; input PCLK, FCLK, TCLK, RESET; @@ -1071,9 +1071,9 @@ endmodule module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3, D4, D5, D6, D7; input TX0, TX1, TX2, TX3; input PCLK, FCLK, TCLK, RESET; @@ -1088,7 +1088,7 @@ output Q; endmodule module IODELAY(DI, SDTAP, VALUE, DLYSTEP, DF, DO); -parameter C_STATIC_DLY = 0; +parameter C_STATIC_DLY = 0; parameter DYN_DLY_EN = "FALSE"; parameter ADAPT_EN = "FALSE"; input DI; @@ -1109,10 +1109,10 @@ output DF0, DF1; input SDTAP0, SDTAP1; input VALUE0,VALUE1; input [7:0] DLYSTEP0,DLYSTEP1; -parameter C_STATIC_DLY_0 = 0; +parameter C_STATIC_DLY_0 = 0; parameter DYN_DLY_EN_0 = "FALSE"; parameter ADAPT_EN_0 = "FALSE"; -parameter C_STATIC_DLY_1 = 0; +parameter C_STATIC_DLY_1 = 0; parameter DYN_DLY_EN_1 = "FALSE"; parameter ADAPT_EN_1 = "FALSE"; endmodule @@ -1127,16 +1127,16 @@ output DF0, DF1, DF2, DF3; input SDTAP0, SDTAP1, SDTAP2, SDTAP3; input VALUE0, VALUE1, VALUE2, VALUE3; input [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3; -parameter C_STATIC_DLY_0 = 0; +parameter C_STATIC_DLY_0 = 0; parameter DYN_DLY_EN_0 = "FALSE"; parameter ADAPT_EN_0 = "FALSE"; -parameter C_STATIC_DLY_1 = 0; +parameter C_STATIC_DLY_1 = 0; parameter DYN_DLY_EN_1 = "FALSE"; parameter ADAPT_EN_1 = "FALSE"; -parameter C_STATIC_DLY_2 = 0; +parameter C_STATIC_DLY_2 = 0; parameter DYN_DLY_EN_2 = "FALSE"; parameter ADAPT_EN_2 = "FALSE"; -parameter C_STATIC_DLY_3 = 0; +parameter C_STATIC_DLY_3 = 0; parameter DYN_DLY_EN_3 = "FALSE"; parameter ADAPT_EN_3 = "FALSE"; endmodule @@ -1151,7 +1151,7 @@ module DCS(CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE, CLKSEL, CLKOUT); input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; -parameter DCS_MODE = "RISING"; +parameter DCS_MODE = "RISING"; endmodule module DDRDLL(CLKIN, STOP, UPDNCNTL, RESET, STEP, LOCK); @@ -1164,7 +1164,7 @@ output LOCK; parameter DLL_FORCE = "FALSE"; parameter CODESCAL = "000"; parameter SCAL_EN = "TRUE"; -parameter DIV_SEL = 1'b0; +parameter DIV_SEL = 1'b0; endmodule module DLLDLY(CLKIN, DLLSTEP, CSTEP, LOADN, MOVE, CLKOUT, FLAG); @@ -1173,8 +1173,8 @@ input [7:0] DLLSTEP, CSTEP; input LOADN,MOVE; output CLKOUT; output FLAG; -parameter DLY_SIGN = 1'b0; -parameter DLY_ADJ = 0; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; parameter DYN_DLY_EN = "FALSE"; parameter ADAPT_EN = "FALSE"; parameter STEP_SEL = 1'b0; @@ -1185,7 +1185,7 @@ input HCLKIN; input RESETN; input CALIB; output CLKOUT; -parameter DIV_MODE = "2"; +parameter DIV_MODE = "2"; endmodule module CLKDIV2(HCLKIN, RESETN, CLKOUT); @@ -1200,20 +1200,20 @@ output CLKOUT; endmodule module OSCA(OSCOUT, OSCEN); -parameter FREQ_DIV = 100; +parameter FREQ_DIV = 100; output OSCOUT; input OSCEN; endmodule module OSCB(OSCOUT, OSCREF, OSCEN, FMODE, RTRIM, RTCTRIM); -parameter FREQ_MODE = "25"; -parameter FREQ_DIV = 10; -parameter DYN_TRIM_EN = "FALSE"; +parameter FREQ_MODE = "25"; +parameter FREQ_DIV = 10; +parameter DYN_TRIM_EN = "FALSE"; output OSCOUT; output OSCREF; input OSCEN, FMODE; input [7:0] RTRIM; -input [5:0] RTCTRIM; +input [5:0] RTCTRIM; endmodule module PLL(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, FBDSEL, IDSEL, MDSEL, MDSEL_FRAC, ODSEL0, ODSEL0_FRAC, ODSEL1, ODSEL2, ODSEL3, ODSEL4, ODSEL5, ODSEL6, DT0, DT1, DT2 @@ -1264,29 +1264,29 @@ output CLKOUT4; output CLKOUT5; output CLKOUT6; output CLKFBOUT; -parameter FCLKIN = "100.0"; +parameter FCLKIN = "100.0"; parameter DYN_IDIV_SEL= "FALSE"; -parameter IDIV_SEL = 1; +parameter IDIV_SEL = 1; parameter DYN_FBDIV_SEL= "FALSE"; -parameter FBDIV_SEL = 1; +parameter FBDIV_SEL = 1; parameter DYN_ODIV0_SEL= "FALSE"; -parameter ODIV0_SEL = 8; +parameter ODIV0_SEL = 8; parameter DYN_ODIV1_SEL= "FALSE"; -parameter ODIV1_SEL = 8; +parameter ODIV1_SEL = 8; parameter DYN_ODIV2_SEL= "FALSE"; -parameter ODIV2_SEL = 8; +parameter ODIV2_SEL = 8; parameter DYN_ODIV3_SEL= "FALSE"; -parameter ODIV3_SEL = 8; +parameter ODIV3_SEL = 8; parameter DYN_ODIV4_SEL= "FALSE"; -parameter ODIV4_SEL = 8; +parameter ODIV4_SEL = 8; parameter DYN_ODIV5_SEL= "FALSE"; -parameter ODIV5_SEL = 8; +parameter ODIV5_SEL = 8; parameter DYN_ODIV6_SEL= "FALSE"; -parameter ODIV6_SEL = 8; +parameter ODIV6_SEL = 8; parameter DYN_MDIV_SEL= "FALSE"; -parameter MDIV_SEL = 8; -parameter MDIV_FRAC_SEL = 0; -parameter ODIV0_FRAC_SEL = 0; +parameter MDIV_SEL = 8; +parameter MDIV_FRAC_SEL = 0; +parameter ODIV0_FRAC_SEL = 0; parameter CLKOUT0_EN = "TRUE"; parameter CLKOUT1_EN = "FALSE"; parameter CLKOUT2_EN = "FALSE"; @@ -1294,19 +1294,19 @@ parameter CLKOUT3_EN = "FALSE"; parameter CLKOUT4_EN = "FALSE"; parameter CLKOUT5_EN = "FALSE"; parameter CLKOUT6_EN = "FALSE"; -parameter CLKFB_SEL = "INTERNAL"; -parameter DYN_DT0_SEL = "FALSE"; -parameter DYN_DT1_SEL = "FALSE"; -parameter DYN_DT2_SEL = "FALSE"; -parameter DYN_DT3_SEL = "FALSE"; -parameter CLKOUT0_DT_DIR = 1'b1; -parameter CLKOUT1_DT_DIR = 1'b1; -parameter CLKOUT2_DT_DIR = 1'b1; -parameter CLKOUT3_DT_DIR = 1'b1; -parameter CLKOUT0_DT_STEP = 0; -parameter CLKOUT1_DT_STEP = 0; -parameter CLKOUT2_DT_STEP = 0; -parameter CLKOUT3_DT_STEP = 0; +parameter CLKFB_SEL = "INTERNAL"; +parameter DYN_DT0_SEL = "FALSE"; +parameter DYN_DT1_SEL = "FALSE"; +parameter DYN_DT2_SEL = "FALSE"; +parameter DYN_DT3_SEL = "FALSE"; +parameter CLKOUT0_DT_DIR = 1'b1; +parameter CLKOUT1_DT_DIR = 1'b1; +parameter CLKOUT2_DT_DIR = 1'b1; +parameter CLKOUT3_DT_DIR = 1'b1; +parameter CLKOUT0_DT_STEP = 0; +parameter CLKOUT1_DT_STEP = 0; +parameter CLKOUT2_DT_STEP = 0; +parameter CLKOUT3_DT_STEP = 0; parameter CLK0_IN_SEL = 1'b0; parameter CLK0_OUT_SEL = 1'b0; parameter CLK1_IN_SEL = 1'b0; @@ -1389,19 +1389,19 @@ output CLKOUT4; output CLKOUT5; output CLKOUT6; output CLKFBOUT; -parameter FCLKIN = "100.0"; -parameter IDIV_SEL = 1; -parameter FBDIV_SEL = 1; -parameter ODIV0_SEL = 8; -parameter ODIV1_SEL = 8; -parameter ODIV2_SEL = 8; -parameter ODIV3_SEL = 8; -parameter ODIV4_SEL = 8; -parameter ODIV5_SEL = 8; -parameter ODIV6_SEL = 8; -parameter MDIV_SEL = 8; -parameter MDIV_FRAC_SEL = 0; -parameter ODIV0_FRAC_SEL = 0; +parameter FCLKIN = "100.0"; +parameter IDIV_SEL = 1; +parameter FBDIV_SEL = 1; +parameter ODIV0_SEL = 8; +parameter ODIV1_SEL = 8; +parameter ODIV2_SEL = 8; +parameter ODIV3_SEL = 8; +parameter ODIV4_SEL = 8; +parameter ODIV5_SEL = 8; +parameter ODIV6_SEL = 8; +parameter MDIV_SEL = 8; +parameter MDIV_FRAC_SEL = 0; +parameter ODIV0_FRAC_SEL = 0; parameter CLKOUT0_EN = "TRUE"; parameter CLKOUT1_EN = "FALSE"; parameter CLKOUT2_EN = "FALSE"; @@ -1409,15 +1409,15 @@ parameter CLKOUT3_EN = "FALSE"; parameter CLKOUT4_EN = "FALSE"; parameter CLKOUT5_EN = "FALSE"; parameter CLKOUT6_EN = "FALSE"; -parameter CLKFB_SEL = "INTERNAL"; -parameter CLKOUT0_DT_DIR = 1'b1; -parameter CLKOUT1_DT_DIR = 1'b1; -parameter CLKOUT2_DT_DIR = 1'b1; -parameter CLKOUT3_DT_DIR = 1'b1; -parameter CLKOUT0_DT_STEP = 0; -parameter CLKOUT1_DT_STEP = 0; -parameter CLKOUT2_DT_STEP = 0; -parameter CLKOUT3_DT_STEP = 0; +parameter CLKFB_SEL = "INTERNAL"; +parameter CLKOUT0_DT_DIR = 1'b1; +parameter CLKOUT1_DT_DIR = 1'b1; +parameter CLKOUT2_DT_DIR = 1'b1; +parameter CLKOUT3_DT_DIR = 1'b1; +parameter CLKOUT0_DT_STEP = 0; +parameter CLKOUT1_DT_STEP = 0; +parameter CLKOUT2_DT_STEP = 0; +parameter CLKOUT3_DT_STEP = 0; parameter CLK0_IN_SEL = 1'b0; parameter CLK0_OUT_SEL = 1'b0; parameter CLK1_IN_SEL = 1'b0; @@ -1500,8 +1500,8 @@ input [15:0] GP_INT; input [ 7:0] DMA_REQ; output [ 7:0] DMA_ACK; output CORE0_WFI_MODE; -input WAKEUP_IN; -output RTC_WAKEUP; +input WAKEUP_IN; +output RTC_WAKEUP; input TEST_CLK; input TEST_MODE; input TEST_RSTN; @@ -1554,7 +1554,7 @@ output [2:0] DDR_HSIZE; output [1:0] DDR_HTRANS; output [63:0] DDR_HWDATA; output DDR_HWRITE; -input TMS_IN; +input TMS_IN; input TRST_IN; input TDI_IN; output TDO_OUT; @@ -1659,14 +1659,14 @@ input RET2N; endmodule module SAMB(SPIAD, LOAD, ADWSEL); -parameter MODE = 2'b00; +parameter MODE = 2'b00; input [23:0] SPIAD; input LOAD; -input ADWSEL; +input ADWSEL; endmodule module OTP(CLK, READ, SHIFT, DOUT); -parameter MODE = 2'b01; +parameter MODE = 2'b01; input CLK, READ, SHIFT; output DOUT; endmodule @@ -1676,11 +1676,11 @@ output RUNNING; output CRCERR; output CRCDONE; output ECCCORR; -output ECCUNCORR; +output ECCUNCORR; output [27:0] ERRLOC; output ECCDEC; output DSRRD; -output DSRWR; +output DSRWR; output ASRRESET; output ASRINC; output REFCLK; @@ -1695,12 +1695,12 @@ output RUNNING; output CRCERR; output CRCDONE; output ECCCORR; -output ECCUNCORR; +output ECCUNCORR; output [26:0] ERR0LOC; output [26:0] ERR1LOC; output ECCDEC; output DSRRD; -output DSRWR; +output DSRWR; output ASRRESET; output ASRINC; output REFCLK; @@ -1715,11 +1715,11 @@ output RUNNING; output CRCERR; output CRCDONE; output ECCCORR; -output ECCUNCORR; +output ECCUNCORR; output [12:0] ERRLOC; output ECCDEC; output DSRRD; -output DSRWR; +output DSRWR; output ASRRESET; output ASRINC; output REFCLK; @@ -1730,17 +1730,17 @@ input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule module SAMBA(SPIAD, LOAD); -parameter MODE = 2'b00; +parameter MODE = 2'b00; input SPIAD; input LOAD; endmodule module LICD(); - parameter STAGE_NUM = 2'b00; - parameter ENCDEC_NUM = 2'b00; - parameter CODE_WIDTH = 2'b00; - parameter INTERLEAVE_EN = 3'b000; - parameter INTERLEAVE_MODE = 3'b000; + parameter STAGE_NUM = 2'b00; + parameter ENCDEC_NUM = 2'b00; + parameter CODE_WIDTH = 2'b00; + parameter INTERLEAVE_EN = 3'b000; + parameter INTERLEAVE_MODE = 3'b000; endmodule module MIPI_DPHY(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N @@ -1764,9 +1764,9 @@ input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; input HSTXD_VLD; input CK0, CK90, CK180, CK270; input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; -input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, +input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, - LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; output [7:0] MRDATA; input MA_INC, MCLK; @@ -1780,269 +1780,269 @@ input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3 input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK; input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK; input ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK; -parameter TX_PLLCLK = "NONE"; -parameter RX_ALIGN_BYTE = 8'b10111000 ; -parameter RX_HS_8BIT_MODE = 1'b0 ; -parameter RX_LANE_ALIGN_EN = 1'b0 ; -parameter TX_HS_8BIT_MODE = 1'b0 ; -parameter HSREG_EN_LN0 = 1'b0; -parameter HSREG_EN_LN1 = 1'b0; -parameter HSREG_EN_LN2 = 1'b0; -parameter HSREG_EN_LN3 = 1'b0; -parameter HSREG_EN_LNCK = 1'b0; -parameter LANE_DIV_SEL = 2'b00; -parameter HSRX_EN = 1'b1 ; -parameter HSRX_LANESEL = 4'b1111 ; -parameter HSRX_LANESEL_CK = 1'b1 ; -parameter HSTX_EN_LN0 = 1'b0 ; -parameter HSTX_EN_LN1 = 1'b0 ; -parameter HSTX_EN_LN2 = 1'b0 ; -parameter HSTX_EN_LN3 = 1'b0 ; -parameter HSTX_EN_LNCK = 1'b0 ; -parameter LPTX_EN_LN0 = 1'b1 ; -parameter LPTX_EN_LN1 = 1'b1 ; -parameter LPTX_EN_LN2 = 1'b1 ; -parameter LPTX_EN_LN3 = 1'b1 ; -parameter LPTX_EN_LNCK = 1'b1 ; -parameter TXDP_EN_LN0 = 1'b0 ; -parameter TXDP_EN_LN1 = 1'b0 ; -parameter TXDP_EN_LN2 = 1'b0 ; -parameter TXDP_EN_LN3 = 1'b0 ; +parameter TX_PLLCLK = "NONE"; +parameter RX_ALIGN_BYTE = 8'b10111000 ; +parameter RX_HS_8BIT_MODE = 1'b0 ; +parameter RX_LANE_ALIGN_EN = 1'b0 ; +parameter TX_HS_8BIT_MODE = 1'b0 ; +parameter HSREG_EN_LN0 = 1'b0; +parameter HSREG_EN_LN1 = 1'b0; +parameter HSREG_EN_LN2 = 1'b0; +parameter HSREG_EN_LN3 = 1'b0; +parameter HSREG_EN_LNCK = 1'b0; +parameter LANE_DIV_SEL = 2'b00; +parameter HSRX_EN = 1'b1 ; +parameter HSRX_LANESEL = 4'b1111 ; +parameter HSRX_LANESEL_CK = 1'b1 ; +parameter HSTX_EN_LN0 = 1'b0 ; +parameter HSTX_EN_LN1 = 1'b0 ; +parameter HSTX_EN_LN2 = 1'b0 ; +parameter HSTX_EN_LN3 = 1'b0 ; +parameter HSTX_EN_LNCK = 1'b0 ; +parameter LPTX_EN_LN0 = 1'b1 ; +parameter LPTX_EN_LN1 = 1'b1 ; +parameter LPTX_EN_LN2 = 1'b1 ; +parameter LPTX_EN_LN3 = 1'b1 ; +parameter LPTX_EN_LNCK = 1'b1 ; +parameter TXDP_EN_LN0 = 1'b0 ; +parameter TXDP_EN_LN1 = 1'b0 ; +parameter TXDP_EN_LN2 = 1'b0 ; +parameter TXDP_EN_LN3 = 1'b0 ; parameter TXDP_EN_LNCK = 1'b0 ; -parameter CKLN_DELAY_EN = 1'b0; -parameter CKLN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DELAY_EN = 1'b0; -parameter D0LN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DESKEW_BYPASS = 1'b0; -parameter D1LN_DELAY_EN = 1'b0; -parameter D1LN_DELAY_OVR_VAL = 7'b0000000; -parameter D1LN_DESKEW_BYPASS = 1'b0; -parameter D2LN_DELAY_EN = 1'b0; -parameter D2LN_DELAY_OVR_VAL = 7'b0000000; -parameter D2LN_DESKEW_BYPASS = 1'b0; -parameter D3LN_DELAY_EN = 1'b0; -parameter D3LN_DELAY_OVR_VAL = 7'b0000000; -parameter D3LN_DESKEW_BYPASS = 1'b0; -parameter DESKEW_EN_LOW_DELAY = 1'b0; -parameter DESKEW_EN_ONE_EDGE = 1'b0; -parameter DESKEW_FAST_LOOP_TIME = 4'b0000; -parameter DESKEW_FAST_MODE = 1'b0; -parameter DESKEW_HALF_OPENING = 6'b010110; -parameter DESKEW_LSB_MODE = 2'b00; -parameter DESKEW_M = 3'b011; -parameter DESKEW_M_TH = 13'b0000110100110; -parameter DESKEW_MAX_SETTING = 7'b0100001; -parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; -parameter DESKEW_RST_BYPASS = 1'b0 ; -parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; -parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; -parameter RX_INVERT = 1'b0 ; -parameter RX_ONE_BYTE0_MATCH = 1'b0 ; -parameter RX_RD_START_DEPTH = 5'b00001; -parameter RX_SYNC_MODE = 1'b0 ; -parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; -parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; -parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter TX_BYPASS_MODE = 1'b0 ; -parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; -parameter TX_OCLK_USE_CIBCLK = 1'b0 ; -parameter TX_RD_START_DEPTH = 5'b00001; -parameter TX_SYNC_MODE = 1'b0 ; -parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter EQ_CS_LANE0 = 3'b100; -parameter EQ_CS_LANE1 = 3'b100; -parameter EQ_CS_LANE2 = 3'b100; -parameter EQ_CS_LANE3 = 3'b100; -parameter EQ_CS_LANECK = 3'b100; -parameter EQ_RS_LANE0 = 3'b100; -parameter EQ_RS_LANE1 = 3'b100; -parameter EQ_RS_LANE2 = 3'b100; -parameter EQ_RS_LANE3 = 3'b100; -parameter EQ_RS_LANECK = 3'b100; -parameter HSCLK_LANE_LN0 = 1'b0; -parameter HSCLK_LANE_LN1 = 1'b0; -parameter HSCLK_LANE_LN2 = 1'b0; -parameter HSCLK_LANE_LN3 = 1'b0; -parameter HSCLK_LANE_LNCK = 1'b1; -parameter ALP_ED_EN_LANE0 = 1'b1 ; -parameter ALP_ED_EN_LANE1 = 1'b1 ; -parameter ALP_ED_EN_LANE2 = 1'b1 ; -parameter ALP_ED_EN_LANE3 = 1'b1 ; -parameter ALP_ED_EN_LANECK = 1'b1 ; -parameter ALP_ED_TST_LANE0 = 1'b0 ; -parameter ALP_ED_TST_LANE1 = 1'b0 ; -parameter ALP_ED_TST_LANE2 = 1'b0 ; -parameter ALP_ED_TST_LANE3 = 1'b0 ; -parameter ALP_ED_TST_LANECK = 1'b0 ; -parameter ALP_EN_LN0 = 1'b0 ; -parameter ALP_EN_LN1 = 1'b0 ; -parameter ALP_EN_LN2 = 1'b0 ; -parameter ALP_EN_LN3 = 1'b0 ; -parameter ALP_EN_LNCK = 1'b0 ; -parameter ALP_HYS_EN_LANE0 = 1'b1 ; -parameter ALP_HYS_EN_LANE1 = 1'b1 ; -parameter ALP_HYS_EN_LANE2 = 1'b1 ; -parameter ALP_HYS_EN_LANE3 = 1'b1 ; -parameter ALP_HYS_EN_LANECK = 1'b1 ; -parameter ALP_TH_LANE0 = 4'b1000 ; -parameter ALP_TH_LANE1 = 4'b1000 ; -parameter ALP_TH_LANE2 = 4'b1000 ; -parameter ALP_TH_LANE3 = 4'b1000 ; -parameter ALP_TH_LANECK = 4'b1000 ; -parameter ANA_BYTECLK_PH = 2'b00 ; -parameter BIT_REVERSE_LN0 = 1'b0 ; -parameter BIT_REVERSE_LN1 = 1'b0 ; -parameter BIT_REVERSE_LN2 = 1'b0 ; -parameter BIT_REVERSE_LN3 = 1'b0 ; -parameter BIT_REVERSE_LNCK = 1'b0 ; -parameter BYPASS_TXHCLKEN = 1'b1 ; -parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; -parameter BYTE_CLK_POLAR = 1'b0 ; -parameter BYTE_REVERSE_LN0 = 1'b0 ; -parameter BYTE_REVERSE_LN1 = 1'b0 ; -parameter BYTE_REVERSE_LN2 = 1'b0 ; -parameter BYTE_REVERSE_LN3 = 1'b0 ; -parameter BYTE_REVERSE_LNCK = 1'b0 ; -parameter EN_CLKB1X = 1'b1 ; -parameter EQ_PBIAS_LANE0 = 4'b1000 ; -parameter EQ_PBIAS_LANE1 = 4'b1000 ; -parameter EQ_PBIAS_LANE2 = 4'b1000 ; -parameter EQ_PBIAS_LANE3 = 4'b1000 ; -parameter EQ_PBIAS_LANECK = 4'b1000 ; -parameter EQ_ZLD_LANE0 = 4'b1000 ; -parameter EQ_ZLD_LANE1 = 4'b1000 ; -parameter EQ_ZLD_LANE2 = 4'b1000 ; -parameter EQ_ZLD_LANE3 = 4'b1000 ; -parameter EQ_ZLD_LANECK = 4'b1000 ; -parameter HIGH_BW_LANE0 = 1'b1 ; -parameter HIGH_BW_LANE1 = 1'b1 ; -parameter HIGH_BW_LANE2 = 1'b1 ; -parameter HIGH_BW_LANE3 = 1'b1 ; -parameter HIGH_BW_LANECK = 1'b1 ; -parameter HSREG_VREF_CTL = 3'b100 ; -parameter HSREG_VREF_EN = 1'b1 ; -parameter HSRX_DLY_CTL_CK = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; -parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; -parameter HSRX_DLY_SEL_LANECK = 1'b0 ; -parameter HSRX_DUTY_LANE0 = 4'b1000 ; -parameter HSRX_DUTY_LANE1 = 4'b1000 ; -parameter HSRX_DUTY_LANE2 = 4'b1000 ; -parameter HSRX_DUTY_LANE3 = 4'b1000 ; -parameter HSRX_DUTY_LANECK = 4'b1000 ; -parameter HSRX_EQ_EN_LANE0 = 1'b1 ; -parameter HSRX_EQ_EN_LANE1 = 1'b1 ; -parameter HSRX_EQ_EN_LANE2 = 1'b1 ; -parameter HSRX_EQ_EN_LANE3 = 1'b1 ; -parameter HSRX_EQ_EN_LANECK = 1'b1 ; -parameter HSRX_IBIAS = 4'b0011 ; -parameter HSRX_IBIAS_TEST_EN = 1'b0 ; -parameter HSRX_IMARG_EN = 1'b0 ; -parameter HSRX_ODT_EN = 1'b1 ; -parameter HSRX_ODT_TST = 4'b0000 ; -parameter HSRX_ODT_TST_CK = 1'b0 ; -parameter HSRX_SEL = 4'b0000 ; -parameter HSRX_STOP_EN = 1'b0 ; -parameter HSRX_TST = 4'b0000 ; -parameter HSRX_TST_CK = 1'b0 ; -parameter HSRX_WAIT4EDGE = 1'b1 ; -parameter HYST_NCTL = 2'b01 ; -parameter HYST_PCTL = 2'b01 ; -parameter IBIAS_TEST_EN = 1'b0 ; -parameter LB_CH_SEL = 1'b0 ; -parameter LB_EN_LN0 = 1'b0 ; -parameter LB_EN_LN1 = 1'b0 ; -parameter LB_EN_LN2 = 1'b0 ; -parameter LB_EN_LN3 = 1'b0 ; -parameter LB_EN_LNCK = 1'b0 ; -parameter LB_POLAR_LN0 = 1'b0 ; -parameter LB_POLAR_LN1 = 1'b0 ; -parameter LB_POLAR_LN2 = 1'b0 ; -parameter LB_POLAR_LN3 = 1'b0 ; -parameter LB_POLAR_LNCK = 1'b0 ; -parameter LOW_LPRX_VTH = 1'b0 ; -parameter LPBK_DATA2TO1 = 4'b0000; -parameter LPBK_DATA2TO1_CK = 1'b0 ; -parameter LPBK_EN = 1'b0 ; -parameter LPBK_SEL = 4'b0000; -parameter LPBKTST_EN = 4'b0000; -parameter LPBKTST_EN_CK = 1'b0 ; -parameter LPRX_EN = 1'b1 ; -parameter LPRX_TST = 4'b0000; -parameter LPRX_TST_CK = 1'b0 ; -parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; -parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; -parameter LPTX_NIMP_LN0 = 3'b100 ; -parameter LPTX_NIMP_LN1 = 3'b100 ; -parameter LPTX_NIMP_LN2 = 3'b100 ; -parameter LPTX_NIMP_LN3 = 3'b100 ; -parameter LPTX_NIMP_LNCK = 3'b100 ; -parameter LPTX_PIMP_LN0 = 3'b100 ; -parameter LPTX_PIMP_LN1 = 3'b100 ; -parameter LPTX_PIMP_LN2 = 3'b100 ; -parameter LPTX_PIMP_LN3 = 3'b100 ; -parameter LPTX_PIMP_LNCK = 3'b100 ; -parameter MIPI_PMA_DIS_N = 1'b1 ; -parameter PGA_BIAS_LANE0 = 4'b1000 ; -parameter PGA_BIAS_LANE1 = 4'b1000 ; -parameter PGA_BIAS_LANE2 = 4'b1000 ; -parameter PGA_BIAS_LANE3 = 4'b1000 ; -parameter PGA_BIAS_LANECK = 4'b1000 ; -parameter PGA_GAIN_LANE0 = 4'b1000 ; -parameter PGA_GAIN_LANE1 = 4'b1000 ; -parameter PGA_GAIN_LANE2 = 4'b1000 ; -parameter PGA_GAIN_LANE3 = 4'b1000 ; -parameter PGA_GAIN_LANECK = 4'b1000 ; -parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; -parameter RX_ODT_TRIM_LANECK = 4'b1000 ; -parameter SLEWN_CTL_LN0 = 4'b1111 ; -parameter SLEWN_CTL_LN1 = 4'b1111 ; -parameter SLEWN_CTL_LN2 = 4'b1111 ; -parameter SLEWN_CTL_LN3 = 4'b1111 ; -parameter SLEWN_CTL_LNCK = 4'b1111 ; -parameter SLEWP_CTL_LN0 = 4'b1111 ; -parameter SLEWP_CTL_LN1 = 4'b1111 ; -parameter SLEWP_CTL_LN2 = 4'b1111 ; -parameter SLEWP_CTL_LN3 = 4'b1111 ; -parameter SLEWP_CTL_LNCK = 4'b1111 ; -parameter STP_UNIT = 2'b01 ; -parameter TERMN_CTL_LN0 = 4'b1000 ; -parameter TERMN_CTL_LN1 = 4'b1000 ; -parameter TERMN_CTL_LN2 = 4'b1000 ; -parameter TERMN_CTL_LN3 = 4'b1000 ; -parameter TERMN_CTL_LNCK = 4'b1000 ; -parameter TERMP_CTL_LN0 = 4'b1000 ; -parameter TERMP_CTL_LN1 = 4'b1000 ; -parameter TERMP_CTL_LN2 = 4'b1000 ; -parameter TERMP_CTL_LN3 = 4'b1000 ; -parameter TERMP_CTL_LNCK = 4'b1000 ; -parameter TEST_EN_LN0 = 1'b0 ; -parameter TEST_EN_LN1 = 1'b0 ; -parameter TEST_EN_LN2 = 1'b0 ; -parameter TEST_EN_LN3 = 1'b0 ; -parameter TEST_EN_LNCK = 1'b0 ; -parameter TEST_N_IMP_LN0 = 1'b0 ; -parameter TEST_N_IMP_LN1 = 1'b0 ; -parameter TEST_N_IMP_LN2 = 1'b0 ; -parameter TEST_N_IMP_LN3 = 1'b0 ; -parameter TEST_N_IMP_LNCK = 1'b0 ; -parameter TEST_P_IMP_LN0 = 1'b0 ; -parameter TEST_P_IMP_LN1 = 1'b0 ; -parameter TEST_P_IMP_LN2 = 1'b0 ; -parameter TEST_P_IMP_LN3 = 1'b0 ; -parameter TEST_P_IMP_LNCK = 1'b0 ; +parameter CKLN_DELAY_EN = 1'b0; +parameter CKLN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DELAY_EN = 1'b0; +parameter D0LN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DESKEW_BYPASS = 1'b0; +parameter D1LN_DELAY_EN = 1'b0; +parameter D1LN_DELAY_OVR_VAL = 7'b0000000; +parameter D1LN_DESKEW_BYPASS = 1'b0; +parameter D2LN_DELAY_EN = 1'b0; +parameter D2LN_DELAY_OVR_VAL = 7'b0000000; +parameter D2LN_DESKEW_BYPASS = 1'b0; +parameter D3LN_DELAY_EN = 1'b0; +parameter D3LN_DELAY_OVR_VAL = 7'b0000000; +parameter D3LN_DESKEW_BYPASS = 1'b0; +parameter DESKEW_EN_LOW_DELAY = 1'b0; +parameter DESKEW_EN_ONE_EDGE = 1'b0; +parameter DESKEW_FAST_LOOP_TIME = 4'b0000; +parameter DESKEW_FAST_MODE = 1'b0; +parameter DESKEW_HALF_OPENING = 6'b010110; +parameter DESKEW_LSB_MODE = 2'b00; +parameter DESKEW_M = 3'b011; +parameter DESKEW_M_TH = 13'b0000110100110; +parameter DESKEW_MAX_SETTING = 7'b0100001; +parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; +parameter DESKEW_RST_BYPASS = 1'b0 ; +parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; +parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; +parameter RX_INVERT = 1'b0 ; +parameter RX_ONE_BYTE0_MATCH = 1'b0 ; +parameter RX_RD_START_DEPTH = 5'b00001; +parameter RX_SYNC_MODE = 1'b0 ; +parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; +parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter TX_BYPASS_MODE = 1'b0 ; +parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; +parameter TX_OCLK_USE_CIBCLK = 1'b0 ; +parameter TX_RD_START_DEPTH = 5'b00001; +parameter TX_SYNC_MODE = 1'b0 ; +parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter EQ_CS_LANE0 = 3'b100; +parameter EQ_CS_LANE1 = 3'b100; +parameter EQ_CS_LANE2 = 3'b100; +parameter EQ_CS_LANE3 = 3'b100; +parameter EQ_CS_LANECK = 3'b100; +parameter EQ_RS_LANE0 = 3'b100; +parameter EQ_RS_LANE1 = 3'b100; +parameter EQ_RS_LANE2 = 3'b100; +parameter EQ_RS_LANE3 = 3'b100; +parameter EQ_RS_LANECK = 3'b100; +parameter HSCLK_LANE_LN0 = 1'b0; +parameter HSCLK_LANE_LN1 = 1'b0; +parameter HSCLK_LANE_LN2 = 1'b0; +parameter HSCLK_LANE_LN3 = 1'b0; +parameter HSCLK_LANE_LNCK = 1'b1; +parameter ALP_ED_EN_LANE0 = 1'b1 ; +parameter ALP_ED_EN_LANE1 = 1'b1 ; +parameter ALP_ED_EN_LANE2 = 1'b1 ; +parameter ALP_ED_EN_LANE3 = 1'b1 ; +parameter ALP_ED_EN_LANECK = 1'b1 ; +parameter ALP_ED_TST_LANE0 = 1'b0 ; +parameter ALP_ED_TST_LANE1 = 1'b0 ; +parameter ALP_ED_TST_LANE2 = 1'b0 ; +parameter ALP_ED_TST_LANE3 = 1'b0 ; +parameter ALP_ED_TST_LANECK = 1'b0 ; +parameter ALP_EN_LN0 = 1'b0 ; +parameter ALP_EN_LN1 = 1'b0 ; +parameter ALP_EN_LN2 = 1'b0 ; +parameter ALP_EN_LN3 = 1'b0 ; +parameter ALP_EN_LNCK = 1'b0 ; +parameter ALP_HYS_EN_LANE0 = 1'b1 ; +parameter ALP_HYS_EN_LANE1 = 1'b1 ; +parameter ALP_HYS_EN_LANE2 = 1'b1 ; +parameter ALP_HYS_EN_LANE3 = 1'b1 ; +parameter ALP_HYS_EN_LANECK = 1'b1 ; +parameter ALP_TH_LANE0 = 4'b1000 ; +parameter ALP_TH_LANE1 = 4'b1000 ; +parameter ALP_TH_LANE2 = 4'b1000 ; +parameter ALP_TH_LANE3 = 4'b1000 ; +parameter ALP_TH_LANECK = 4'b1000 ; +parameter ANA_BYTECLK_PH = 2'b00 ; +parameter BIT_REVERSE_LN0 = 1'b0 ; +parameter BIT_REVERSE_LN1 = 1'b0 ; +parameter BIT_REVERSE_LN2 = 1'b0 ; +parameter BIT_REVERSE_LN3 = 1'b0 ; +parameter BIT_REVERSE_LNCK = 1'b0 ; +parameter BYPASS_TXHCLKEN = 1'b1 ; +parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; +parameter BYTE_CLK_POLAR = 1'b0 ; +parameter BYTE_REVERSE_LN0 = 1'b0 ; +parameter BYTE_REVERSE_LN1 = 1'b0 ; +parameter BYTE_REVERSE_LN2 = 1'b0 ; +parameter BYTE_REVERSE_LN3 = 1'b0 ; +parameter BYTE_REVERSE_LNCK = 1'b0 ; +parameter EN_CLKB1X = 1'b1 ; +parameter EQ_PBIAS_LANE0 = 4'b1000 ; +parameter EQ_PBIAS_LANE1 = 4'b1000 ; +parameter EQ_PBIAS_LANE2 = 4'b1000 ; +parameter EQ_PBIAS_LANE3 = 4'b1000 ; +parameter EQ_PBIAS_LANECK = 4'b1000 ; +parameter EQ_ZLD_LANE0 = 4'b1000 ; +parameter EQ_ZLD_LANE1 = 4'b1000 ; +parameter EQ_ZLD_LANE2 = 4'b1000 ; +parameter EQ_ZLD_LANE3 = 4'b1000 ; +parameter EQ_ZLD_LANECK = 4'b1000 ; +parameter HIGH_BW_LANE0 = 1'b1 ; +parameter HIGH_BW_LANE1 = 1'b1 ; +parameter HIGH_BW_LANE2 = 1'b1 ; +parameter HIGH_BW_LANE3 = 1'b1 ; +parameter HIGH_BW_LANECK = 1'b1 ; +parameter HSREG_VREF_CTL = 3'b100 ; +parameter HSREG_VREF_EN = 1'b1 ; +parameter HSRX_DLY_CTL_CK = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; +parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; +parameter HSRX_DLY_SEL_LANECK = 1'b0 ; +parameter HSRX_DUTY_LANE0 = 4'b1000 ; +parameter HSRX_DUTY_LANE1 = 4'b1000 ; +parameter HSRX_DUTY_LANE2 = 4'b1000 ; +parameter HSRX_DUTY_LANE3 = 4'b1000 ; +parameter HSRX_DUTY_LANECK = 4'b1000 ; +parameter HSRX_EQ_EN_LANE0 = 1'b1 ; +parameter HSRX_EQ_EN_LANE1 = 1'b1 ; +parameter HSRX_EQ_EN_LANE2 = 1'b1 ; +parameter HSRX_EQ_EN_LANE3 = 1'b1 ; +parameter HSRX_EQ_EN_LANECK = 1'b1 ; +parameter HSRX_IBIAS = 4'b0011 ; +parameter HSRX_IBIAS_TEST_EN = 1'b0 ; +parameter HSRX_IMARG_EN = 1'b0 ; +parameter HSRX_ODT_EN = 1'b1 ; +parameter HSRX_ODT_TST = 4'b0000 ; +parameter HSRX_ODT_TST_CK = 1'b0 ; +parameter HSRX_SEL = 4'b0000 ; +parameter HSRX_STOP_EN = 1'b0 ; +parameter HSRX_TST = 4'b0000 ; +parameter HSRX_TST_CK = 1'b0 ; +parameter HSRX_WAIT4EDGE = 1'b1 ; +parameter HYST_NCTL = 2'b01 ; +parameter HYST_PCTL = 2'b01 ; +parameter IBIAS_TEST_EN = 1'b0 ; +parameter LB_CH_SEL = 1'b0 ; +parameter LB_EN_LN0 = 1'b0 ; +parameter LB_EN_LN1 = 1'b0 ; +parameter LB_EN_LN2 = 1'b0 ; +parameter LB_EN_LN3 = 1'b0 ; +parameter LB_EN_LNCK = 1'b0 ; +parameter LB_POLAR_LN0 = 1'b0 ; +parameter LB_POLAR_LN1 = 1'b0 ; +parameter LB_POLAR_LN2 = 1'b0 ; +parameter LB_POLAR_LN3 = 1'b0 ; +parameter LB_POLAR_LNCK = 1'b0 ; +parameter LOW_LPRX_VTH = 1'b0 ; +parameter LPBK_DATA2TO1 = 4'b0000; +parameter LPBK_DATA2TO1_CK = 1'b0 ; +parameter LPBK_EN = 1'b0 ; +parameter LPBK_SEL = 4'b0000; +parameter LPBKTST_EN = 4'b0000; +parameter LPBKTST_EN_CK = 1'b0 ; +parameter LPRX_EN = 1'b1 ; +parameter LPRX_TST = 4'b0000; +parameter LPRX_TST_CK = 1'b0 ; +parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; +parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; +parameter LPTX_NIMP_LN0 = 3'b100 ; +parameter LPTX_NIMP_LN1 = 3'b100 ; +parameter LPTX_NIMP_LN2 = 3'b100 ; +parameter LPTX_NIMP_LN3 = 3'b100 ; +parameter LPTX_NIMP_LNCK = 3'b100 ; +parameter LPTX_PIMP_LN0 = 3'b100 ; +parameter LPTX_PIMP_LN1 = 3'b100 ; +parameter LPTX_PIMP_LN2 = 3'b100 ; +parameter LPTX_PIMP_LN3 = 3'b100 ; +parameter LPTX_PIMP_LNCK = 3'b100 ; +parameter MIPI_PMA_DIS_N = 1'b1 ; +parameter PGA_BIAS_LANE0 = 4'b1000 ; +parameter PGA_BIAS_LANE1 = 4'b1000 ; +parameter PGA_BIAS_LANE2 = 4'b1000 ; +parameter PGA_BIAS_LANE3 = 4'b1000 ; +parameter PGA_BIAS_LANECK = 4'b1000 ; +parameter PGA_GAIN_LANE0 = 4'b1000 ; +parameter PGA_GAIN_LANE1 = 4'b1000 ; +parameter PGA_GAIN_LANE2 = 4'b1000 ; +parameter PGA_GAIN_LANE3 = 4'b1000 ; +parameter PGA_GAIN_LANECK = 4'b1000 ; +parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; +parameter RX_ODT_TRIM_LANECK = 4'b1000 ; +parameter SLEWN_CTL_LN0 = 4'b1111 ; +parameter SLEWN_CTL_LN1 = 4'b1111 ; +parameter SLEWN_CTL_LN2 = 4'b1111 ; +parameter SLEWN_CTL_LN3 = 4'b1111 ; +parameter SLEWN_CTL_LNCK = 4'b1111 ; +parameter SLEWP_CTL_LN0 = 4'b1111 ; +parameter SLEWP_CTL_LN1 = 4'b1111 ; +parameter SLEWP_CTL_LN2 = 4'b1111 ; +parameter SLEWP_CTL_LN3 = 4'b1111 ; +parameter SLEWP_CTL_LNCK = 4'b1111 ; +parameter STP_UNIT = 2'b01 ; +parameter TERMN_CTL_LN0 = 4'b1000 ; +parameter TERMN_CTL_LN1 = 4'b1000 ; +parameter TERMN_CTL_LN2 = 4'b1000 ; +parameter TERMN_CTL_LN3 = 4'b1000 ; +parameter TERMN_CTL_LNCK = 4'b1000 ; +parameter TERMP_CTL_LN0 = 4'b1000 ; +parameter TERMP_CTL_LN1 = 4'b1000 ; +parameter TERMP_CTL_LN2 = 4'b1000 ; +parameter TERMP_CTL_LN3 = 4'b1000 ; +parameter TERMP_CTL_LNCK = 4'b1000 ; +parameter TEST_EN_LN0 = 1'b0 ; +parameter TEST_EN_LN1 = 1'b0 ; +parameter TEST_EN_LN2 = 1'b0 ; +parameter TEST_EN_LN3 = 1'b0 ; +parameter TEST_EN_LNCK = 1'b0 ; +parameter TEST_N_IMP_LN0 = 1'b0 ; +parameter TEST_N_IMP_LN1 = 1'b0 ; +parameter TEST_N_IMP_LN2 = 1'b0 ; +parameter TEST_N_IMP_LN3 = 1'b0 ; +parameter TEST_N_IMP_LNCK = 1'b0 ; +parameter TEST_P_IMP_LN0 = 1'b0 ; +parameter TEST_P_IMP_LN1 = 1'b0 ; +parameter TEST_P_IMP_LN2 = 1'b0 ; +parameter TEST_P_IMP_LN3 = 1'b0 ; +parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule module MIPI_DPHYA(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N @@ -2066,9 +2066,9 @@ input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; input HSTXD_VLD; input CK0, CK90, CK180, CK270; input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; -input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, +input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, - LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; output [7:0] MRDATA; input MA_INC, MCLK; @@ -2083,271 +2083,271 @@ input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3 input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK; input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK; input ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK; -parameter TX_PLLCLK = "NONE"; -parameter RX_ALIGN_BYTE = 8'b10111000 ; -parameter RX_HS_8BIT_MODE = 1'b0 ; -parameter RX_LANE_ALIGN_EN = 1'b0 ; -parameter TX_HS_8BIT_MODE = 1'b0 ; -parameter HSREG_EN_LN0 = 1'b0; -parameter HSREG_EN_LN1 = 1'b0; -parameter HSREG_EN_LN2 = 1'b0; -parameter HSREG_EN_LN3 = 1'b0; -parameter HSREG_EN_LNCK = 1'b0; -parameter LANE_DIV_SEL = 2'b00; -parameter HSRX_EN = 1'b1 ; -parameter HSRX_LANESEL = 4'b1111 ; -parameter HSRX_LANESEL_CK = 1'b1 ; -parameter HSTX_EN_LN0 = 1'b0 ; -parameter HSTX_EN_LN1 = 1'b0 ; -parameter HSTX_EN_LN2 = 1'b0 ; -parameter HSTX_EN_LN3 = 1'b0 ; -parameter HSTX_EN_LNCK = 1'b0 ; -parameter LPTX_EN_LN0 = 1'b1 ; -parameter LPTX_EN_LN1 = 1'b1 ; -parameter LPTX_EN_LN2 = 1'b1 ; -parameter LPTX_EN_LN3 = 1'b1 ; -parameter LPTX_EN_LNCK = 1'b1 ; -parameter TXDP_EN_LN0 = 1'b0 ; -parameter TXDP_EN_LN1 = 1'b0 ; -parameter TXDP_EN_LN2 = 1'b0 ; -parameter TXDP_EN_LN3 = 1'b0 ; +parameter TX_PLLCLK = "NONE"; +parameter RX_ALIGN_BYTE = 8'b10111000 ; +parameter RX_HS_8BIT_MODE = 1'b0 ; +parameter RX_LANE_ALIGN_EN = 1'b0 ; +parameter TX_HS_8BIT_MODE = 1'b0 ; +parameter HSREG_EN_LN0 = 1'b0; +parameter HSREG_EN_LN1 = 1'b0; +parameter HSREG_EN_LN2 = 1'b0; +parameter HSREG_EN_LN3 = 1'b0; +parameter HSREG_EN_LNCK = 1'b0; +parameter LANE_DIV_SEL = 2'b00; +parameter HSRX_EN = 1'b1 ; +parameter HSRX_LANESEL = 4'b1111 ; +parameter HSRX_LANESEL_CK = 1'b1 ; +parameter HSTX_EN_LN0 = 1'b0 ; +parameter HSTX_EN_LN1 = 1'b0 ; +parameter HSTX_EN_LN2 = 1'b0 ; +parameter HSTX_EN_LN3 = 1'b0 ; +parameter HSTX_EN_LNCK = 1'b0 ; +parameter LPTX_EN_LN0 = 1'b1 ; +parameter LPTX_EN_LN1 = 1'b1 ; +parameter LPTX_EN_LN2 = 1'b1 ; +parameter LPTX_EN_LN3 = 1'b1 ; +parameter LPTX_EN_LNCK = 1'b1 ; +parameter TXDP_EN_LN0 = 1'b0 ; +parameter TXDP_EN_LN1 = 1'b0 ; +parameter TXDP_EN_LN2 = 1'b0 ; +parameter TXDP_EN_LN3 = 1'b0 ; parameter TXDP_EN_LNCK = 1'b0 ; parameter SPLL_DIV_SEL = 2'b00; parameter DPHY_CK_SEL = 2'b01; -parameter CKLN_DELAY_EN = 1'b0; -parameter CKLN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DELAY_EN = 1'b0; -parameter D0LN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DESKEW_BYPASS = 1'b0; -parameter D1LN_DELAY_EN = 1'b0; -parameter D1LN_DELAY_OVR_VAL = 7'b0000000; -parameter D1LN_DESKEW_BYPASS = 1'b0; -parameter D2LN_DELAY_EN = 1'b0; -parameter D2LN_DELAY_OVR_VAL = 7'b0000000; -parameter D2LN_DESKEW_BYPASS = 1'b0; -parameter D3LN_DELAY_EN = 1'b0; -parameter D3LN_DELAY_OVR_VAL = 7'b0000000; -parameter D3LN_DESKEW_BYPASS = 1'b0; -parameter DESKEW_EN_LOW_DELAY = 1'b0; -parameter DESKEW_EN_ONE_EDGE = 1'b0; -parameter DESKEW_FAST_LOOP_TIME = 4'b0000; -parameter DESKEW_FAST_MODE = 1'b0; -parameter DESKEW_HALF_OPENING = 6'b010110; -parameter DESKEW_LSB_MODE = 2'b00; -parameter DESKEW_M = 3'b011; -parameter DESKEW_M_TH = 13'b0000110100110; -parameter DESKEW_MAX_SETTING = 7'b0100001; -parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; -parameter DESKEW_RST_BYPASS = 1'b0 ; -parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; -parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; -parameter RX_INVERT = 1'b0 ; -parameter RX_ONE_BYTE0_MATCH = 1'b0 ; -parameter RX_RD_START_DEPTH = 5'b00001; -parameter RX_SYNC_MODE = 1'b0 ; -parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; -parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; -parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter TX_BYPASS_MODE = 1'b0 ; -parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; -parameter TX_OCLK_USE_CIBCLK = 1'b0 ; -parameter TX_RD_START_DEPTH = 5'b00001; -parameter TX_SYNC_MODE = 1'b0 ; -parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter EQ_CS_LANE0 = 3'b100; -parameter EQ_CS_LANE1 = 3'b100; -parameter EQ_CS_LANE2 = 3'b100; -parameter EQ_CS_LANE3 = 3'b100; -parameter EQ_CS_LANECK = 3'b100; -parameter EQ_RS_LANE0 = 3'b100; -parameter EQ_RS_LANE1 = 3'b100; -parameter EQ_RS_LANE2 = 3'b100; -parameter EQ_RS_LANE3 = 3'b100; -parameter EQ_RS_LANECK = 3'b100; -parameter HSCLK_LANE_LN0 = 1'b0; -parameter HSCLK_LANE_LN1 = 1'b0; -parameter HSCLK_LANE_LN2 = 1'b0; -parameter HSCLK_LANE_LN3 = 1'b0; -parameter HSCLK_LANE_LNCK = 1'b1; -parameter ALP_ED_EN_LANE0 = 1'b1 ; -parameter ALP_ED_EN_LANE1 = 1'b1 ; -parameter ALP_ED_EN_LANE2 = 1'b1 ; -parameter ALP_ED_EN_LANE3 = 1'b1 ; -parameter ALP_ED_EN_LANECK = 1'b1 ; -parameter ALP_ED_TST_LANE0 = 1'b0 ; -parameter ALP_ED_TST_LANE1 = 1'b0 ; -parameter ALP_ED_TST_LANE2 = 1'b0 ; -parameter ALP_ED_TST_LANE3 = 1'b0 ; -parameter ALP_ED_TST_LANECK = 1'b0 ; -parameter ALP_EN_LN0 = 1'b0 ; -parameter ALP_EN_LN1 = 1'b0 ; -parameter ALP_EN_LN2 = 1'b0 ; -parameter ALP_EN_LN3 = 1'b0 ; -parameter ALP_EN_LNCK = 1'b0 ; -parameter ALP_HYS_EN_LANE0 = 1'b1 ; -parameter ALP_HYS_EN_LANE1 = 1'b1 ; -parameter ALP_HYS_EN_LANE2 = 1'b1 ; -parameter ALP_HYS_EN_LANE3 = 1'b1 ; -parameter ALP_HYS_EN_LANECK = 1'b1 ; -parameter ALP_TH_LANE0 = 4'b1000 ; -parameter ALP_TH_LANE1 = 4'b1000 ; -parameter ALP_TH_LANE2 = 4'b1000 ; -parameter ALP_TH_LANE3 = 4'b1000 ; -parameter ALP_TH_LANECK = 4'b1000 ; -parameter ANA_BYTECLK_PH = 2'b00 ; -parameter BIT_REVERSE_LN0 = 1'b0 ; -parameter BIT_REVERSE_LN1 = 1'b0 ; -parameter BIT_REVERSE_LN2 = 1'b0 ; -parameter BIT_REVERSE_LN3 = 1'b0 ; -parameter BIT_REVERSE_LNCK = 1'b0 ; -parameter BYPASS_TXHCLKEN = 1'b1 ; -parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; -parameter BYTE_CLK_POLAR = 1'b0 ; -parameter BYTE_REVERSE_LN0 = 1'b0 ; -parameter BYTE_REVERSE_LN1 = 1'b0 ; -parameter BYTE_REVERSE_LN2 = 1'b0 ; -parameter BYTE_REVERSE_LN3 = 1'b0 ; -parameter BYTE_REVERSE_LNCK = 1'b0 ; -parameter EN_CLKB1X = 1'b1 ; -parameter EQ_PBIAS_LANE0 = 4'b1000 ; -parameter EQ_PBIAS_LANE1 = 4'b1000 ; -parameter EQ_PBIAS_LANE2 = 4'b1000 ; -parameter EQ_PBIAS_LANE3 = 4'b1000 ; -parameter EQ_PBIAS_LANECK = 4'b1000 ; -parameter EQ_ZLD_LANE0 = 4'b1000 ; -parameter EQ_ZLD_LANE1 = 4'b1000 ; -parameter EQ_ZLD_LANE2 = 4'b1000 ; -parameter EQ_ZLD_LANE3 = 4'b1000 ; -parameter EQ_ZLD_LANECK = 4'b1000 ; -parameter HIGH_BW_LANE0 = 1'b1 ; -parameter HIGH_BW_LANE1 = 1'b1 ; -parameter HIGH_BW_LANE2 = 1'b1 ; -parameter HIGH_BW_LANE3 = 1'b1 ; -parameter HIGH_BW_LANECK = 1'b1 ; -parameter HSREG_VREF_CTL = 3'b100 ; -parameter HSREG_VREF_EN = 1'b1 ; -parameter HSRX_DLY_CTL_CK = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; -parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; -parameter HSRX_DLY_SEL_LANECK = 1'b0 ; -parameter HSRX_DUTY_LANE0 = 4'b1000 ; -parameter HSRX_DUTY_LANE1 = 4'b1000 ; -parameter HSRX_DUTY_LANE2 = 4'b1000 ; -parameter HSRX_DUTY_LANE3 = 4'b1000 ; -parameter HSRX_DUTY_LANECK = 4'b1000 ; -parameter HSRX_EQ_EN_LANE0 = 1'b1 ; -parameter HSRX_EQ_EN_LANE1 = 1'b1 ; -parameter HSRX_EQ_EN_LANE2 = 1'b1 ; -parameter HSRX_EQ_EN_LANE3 = 1'b1 ; -parameter HSRX_EQ_EN_LANECK = 1'b1 ; -parameter HSRX_IBIAS = 4'b0011 ; -parameter HSRX_IBIAS_TEST_EN = 1'b0 ; -parameter HSRX_IMARG_EN = 1'b0 ; -parameter HSRX_ODT_EN = 1'b1 ; -parameter HSRX_ODT_TST = 4'b0000 ; -parameter HSRX_ODT_TST_CK = 1'b0 ; -parameter HSRX_SEL = 4'b0000 ; -parameter HSRX_STOP_EN = 1'b0 ; -parameter HSRX_TST = 4'b0000 ; -parameter HSRX_TST_CK = 1'b0 ; -parameter HSRX_WAIT4EDGE = 1'b1 ; -parameter HYST_NCTL = 2'b01 ; -parameter HYST_PCTL = 2'b01 ; -parameter IBIAS_TEST_EN = 1'b0 ; -parameter LB_CH_SEL = 1'b0 ; -parameter LB_EN_LN0 = 1'b0 ; -parameter LB_EN_LN1 = 1'b0 ; -parameter LB_EN_LN2 = 1'b0 ; -parameter LB_EN_LN3 = 1'b0 ; -parameter LB_EN_LNCK = 1'b0 ; -parameter LB_POLAR_LN0 = 1'b0 ; -parameter LB_POLAR_LN1 = 1'b0 ; -parameter LB_POLAR_LN2 = 1'b0 ; -parameter LB_POLAR_LN3 = 1'b0 ; -parameter LB_POLAR_LNCK = 1'b0 ; -parameter LOW_LPRX_VTH = 1'b0 ; -parameter LPBK_DATA2TO1 = 4'b0000; -parameter LPBK_DATA2TO1_CK = 1'b0 ; -parameter LPBK_EN = 1'b0 ; -parameter LPBK_SEL = 4'b0000; -parameter LPBKTST_EN = 4'b0000; -parameter LPBKTST_EN_CK = 1'b0 ; -parameter LPRX_EN = 1'b1 ; -parameter LPRX_TST = 4'b0000; -parameter LPRX_TST_CK = 1'b0 ; -parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; -parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; -parameter LPTX_NIMP_LN0 = 3'b100 ; -parameter LPTX_NIMP_LN1 = 3'b100 ; -parameter LPTX_NIMP_LN2 = 3'b100 ; -parameter LPTX_NIMP_LN3 = 3'b100 ; -parameter LPTX_NIMP_LNCK = 3'b100 ; -parameter LPTX_PIMP_LN0 = 3'b100 ; -parameter LPTX_PIMP_LN1 = 3'b100 ; -parameter LPTX_PIMP_LN2 = 3'b100 ; -parameter LPTX_PIMP_LN3 = 3'b100 ; -parameter LPTX_PIMP_LNCK = 3'b100 ; -parameter MIPI_PMA_DIS_N = 1'b1 ; -parameter PGA_BIAS_LANE0 = 4'b1000 ; -parameter PGA_BIAS_LANE1 = 4'b1000 ; -parameter PGA_BIAS_LANE2 = 4'b1000 ; -parameter PGA_BIAS_LANE3 = 4'b1000 ; -parameter PGA_BIAS_LANECK = 4'b1000 ; -parameter PGA_GAIN_LANE0 = 4'b1000 ; -parameter PGA_GAIN_LANE1 = 4'b1000 ; -parameter PGA_GAIN_LANE2 = 4'b1000 ; -parameter PGA_GAIN_LANE3 = 4'b1000 ; -parameter PGA_GAIN_LANECK = 4'b1000 ; -parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; -parameter RX_ODT_TRIM_LANECK = 4'b1000 ; -parameter SLEWN_CTL_LN0 = 4'b1111 ; -parameter SLEWN_CTL_LN1 = 4'b1111 ; -parameter SLEWN_CTL_LN2 = 4'b1111 ; -parameter SLEWN_CTL_LN3 = 4'b1111 ; -parameter SLEWN_CTL_LNCK = 4'b1111 ; -parameter SLEWP_CTL_LN0 = 4'b1111 ; -parameter SLEWP_CTL_LN1 = 4'b1111 ; -parameter SLEWP_CTL_LN2 = 4'b1111 ; -parameter SLEWP_CTL_LN3 = 4'b1111 ; -parameter SLEWP_CTL_LNCK = 4'b1111 ; -parameter STP_UNIT = 2'b01 ; -parameter TERMN_CTL_LN0 = 4'b1000 ; -parameter TERMN_CTL_LN1 = 4'b1000 ; -parameter TERMN_CTL_LN2 = 4'b1000 ; -parameter TERMN_CTL_LN3 = 4'b1000 ; -parameter TERMN_CTL_LNCK = 4'b1000 ; -parameter TERMP_CTL_LN0 = 4'b1000 ; -parameter TERMP_CTL_LN1 = 4'b1000 ; -parameter TERMP_CTL_LN2 = 4'b1000 ; -parameter TERMP_CTL_LN3 = 4'b1000 ; -parameter TERMP_CTL_LNCK = 4'b1000 ; -parameter TEST_EN_LN0 = 1'b0 ; -parameter TEST_EN_LN1 = 1'b0 ; -parameter TEST_EN_LN2 = 1'b0 ; -parameter TEST_EN_LN3 = 1'b0 ; -parameter TEST_EN_LNCK = 1'b0 ; -parameter TEST_N_IMP_LN0 = 1'b0 ; -parameter TEST_N_IMP_LN1 = 1'b0 ; -parameter TEST_N_IMP_LN2 = 1'b0 ; -parameter TEST_N_IMP_LN3 = 1'b0 ; -parameter TEST_N_IMP_LNCK = 1'b0 ; -parameter TEST_P_IMP_LN0 = 1'b0 ; -parameter TEST_P_IMP_LN1 = 1'b0 ; -parameter TEST_P_IMP_LN2 = 1'b0 ; -parameter TEST_P_IMP_LN3 = 1'b0 ; -parameter TEST_P_IMP_LNCK = 1'b0 ; +parameter CKLN_DELAY_EN = 1'b0; +parameter CKLN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DELAY_EN = 1'b0; +parameter D0LN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DESKEW_BYPASS = 1'b0; +parameter D1LN_DELAY_EN = 1'b0; +parameter D1LN_DELAY_OVR_VAL = 7'b0000000; +parameter D1LN_DESKEW_BYPASS = 1'b0; +parameter D2LN_DELAY_EN = 1'b0; +parameter D2LN_DELAY_OVR_VAL = 7'b0000000; +parameter D2LN_DESKEW_BYPASS = 1'b0; +parameter D3LN_DELAY_EN = 1'b0; +parameter D3LN_DELAY_OVR_VAL = 7'b0000000; +parameter D3LN_DESKEW_BYPASS = 1'b0; +parameter DESKEW_EN_LOW_DELAY = 1'b0; +parameter DESKEW_EN_ONE_EDGE = 1'b0; +parameter DESKEW_FAST_LOOP_TIME = 4'b0000; +parameter DESKEW_FAST_MODE = 1'b0; +parameter DESKEW_HALF_OPENING = 6'b010110; +parameter DESKEW_LSB_MODE = 2'b00; +parameter DESKEW_M = 3'b011; +parameter DESKEW_M_TH = 13'b0000110100110; +parameter DESKEW_MAX_SETTING = 7'b0100001; +parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; +parameter DESKEW_RST_BYPASS = 1'b0 ; +parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; +parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; +parameter RX_INVERT = 1'b0 ; +parameter RX_ONE_BYTE0_MATCH = 1'b0 ; +parameter RX_RD_START_DEPTH = 5'b00001; +parameter RX_SYNC_MODE = 1'b0 ; +parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; +parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter TX_BYPASS_MODE = 1'b0 ; +parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; +parameter TX_OCLK_USE_CIBCLK = 1'b0 ; +parameter TX_RD_START_DEPTH = 5'b00001; +parameter TX_SYNC_MODE = 1'b0 ; +parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter EQ_CS_LANE0 = 3'b100; +parameter EQ_CS_LANE1 = 3'b100; +parameter EQ_CS_LANE2 = 3'b100; +parameter EQ_CS_LANE3 = 3'b100; +parameter EQ_CS_LANECK = 3'b100; +parameter EQ_RS_LANE0 = 3'b100; +parameter EQ_RS_LANE1 = 3'b100; +parameter EQ_RS_LANE2 = 3'b100; +parameter EQ_RS_LANE3 = 3'b100; +parameter EQ_RS_LANECK = 3'b100; +parameter HSCLK_LANE_LN0 = 1'b0; +parameter HSCLK_LANE_LN1 = 1'b0; +parameter HSCLK_LANE_LN2 = 1'b0; +parameter HSCLK_LANE_LN3 = 1'b0; +parameter HSCLK_LANE_LNCK = 1'b1; +parameter ALP_ED_EN_LANE0 = 1'b1 ; +parameter ALP_ED_EN_LANE1 = 1'b1 ; +parameter ALP_ED_EN_LANE2 = 1'b1 ; +parameter ALP_ED_EN_LANE3 = 1'b1 ; +parameter ALP_ED_EN_LANECK = 1'b1 ; +parameter ALP_ED_TST_LANE0 = 1'b0 ; +parameter ALP_ED_TST_LANE1 = 1'b0 ; +parameter ALP_ED_TST_LANE2 = 1'b0 ; +parameter ALP_ED_TST_LANE3 = 1'b0 ; +parameter ALP_ED_TST_LANECK = 1'b0 ; +parameter ALP_EN_LN0 = 1'b0 ; +parameter ALP_EN_LN1 = 1'b0 ; +parameter ALP_EN_LN2 = 1'b0 ; +parameter ALP_EN_LN3 = 1'b0 ; +parameter ALP_EN_LNCK = 1'b0 ; +parameter ALP_HYS_EN_LANE0 = 1'b1 ; +parameter ALP_HYS_EN_LANE1 = 1'b1 ; +parameter ALP_HYS_EN_LANE2 = 1'b1 ; +parameter ALP_HYS_EN_LANE3 = 1'b1 ; +parameter ALP_HYS_EN_LANECK = 1'b1 ; +parameter ALP_TH_LANE0 = 4'b1000 ; +parameter ALP_TH_LANE1 = 4'b1000 ; +parameter ALP_TH_LANE2 = 4'b1000 ; +parameter ALP_TH_LANE3 = 4'b1000 ; +parameter ALP_TH_LANECK = 4'b1000 ; +parameter ANA_BYTECLK_PH = 2'b00 ; +parameter BIT_REVERSE_LN0 = 1'b0 ; +parameter BIT_REVERSE_LN1 = 1'b0 ; +parameter BIT_REVERSE_LN2 = 1'b0 ; +parameter BIT_REVERSE_LN3 = 1'b0 ; +parameter BIT_REVERSE_LNCK = 1'b0 ; +parameter BYPASS_TXHCLKEN = 1'b1 ; +parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; +parameter BYTE_CLK_POLAR = 1'b0 ; +parameter BYTE_REVERSE_LN0 = 1'b0 ; +parameter BYTE_REVERSE_LN1 = 1'b0 ; +parameter BYTE_REVERSE_LN2 = 1'b0 ; +parameter BYTE_REVERSE_LN3 = 1'b0 ; +parameter BYTE_REVERSE_LNCK = 1'b0 ; +parameter EN_CLKB1X = 1'b1 ; +parameter EQ_PBIAS_LANE0 = 4'b1000 ; +parameter EQ_PBIAS_LANE1 = 4'b1000 ; +parameter EQ_PBIAS_LANE2 = 4'b1000 ; +parameter EQ_PBIAS_LANE3 = 4'b1000 ; +parameter EQ_PBIAS_LANECK = 4'b1000 ; +parameter EQ_ZLD_LANE0 = 4'b1000 ; +parameter EQ_ZLD_LANE1 = 4'b1000 ; +parameter EQ_ZLD_LANE2 = 4'b1000 ; +parameter EQ_ZLD_LANE3 = 4'b1000 ; +parameter EQ_ZLD_LANECK = 4'b1000 ; +parameter HIGH_BW_LANE0 = 1'b1 ; +parameter HIGH_BW_LANE1 = 1'b1 ; +parameter HIGH_BW_LANE2 = 1'b1 ; +parameter HIGH_BW_LANE3 = 1'b1 ; +parameter HIGH_BW_LANECK = 1'b1 ; +parameter HSREG_VREF_CTL = 3'b100 ; +parameter HSREG_VREF_EN = 1'b1 ; +parameter HSRX_DLY_CTL_CK = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; +parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; +parameter HSRX_DLY_SEL_LANECK = 1'b0 ; +parameter HSRX_DUTY_LANE0 = 4'b1000 ; +parameter HSRX_DUTY_LANE1 = 4'b1000 ; +parameter HSRX_DUTY_LANE2 = 4'b1000 ; +parameter HSRX_DUTY_LANE3 = 4'b1000 ; +parameter HSRX_DUTY_LANECK = 4'b1000 ; +parameter HSRX_EQ_EN_LANE0 = 1'b1 ; +parameter HSRX_EQ_EN_LANE1 = 1'b1 ; +parameter HSRX_EQ_EN_LANE2 = 1'b1 ; +parameter HSRX_EQ_EN_LANE3 = 1'b1 ; +parameter HSRX_EQ_EN_LANECK = 1'b1 ; +parameter HSRX_IBIAS = 4'b0011 ; +parameter HSRX_IBIAS_TEST_EN = 1'b0 ; +parameter HSRX_IMARG_EN = 1'b0 ; +parameter HSRX_ODT_EN = 1'b1 ; +parameter HSRX_ODT_TST = 4'b0000 ; +parameter HSRX_ODT_TST_CK = 1'b0 ; +parameter HSRX_SEL = 4'b0000 ; +parameter HSRX_STOP_EN = 1'b0 ; +parameter HSRX_TST = 4'b0000 ; +parameter HSRX_TST_CK = 1'b0 ; +parameter HSRX_WAIT4EDGE = 1'b1 ; +parameter HYST_NCTL = 2'b01 ; +parameter HYST_PCTL = 2'b01 ; +parameter IBIAS_TEST_EN = 1'b0 ; +parameter LB_CH_SEL = 1'b0 ; +parameter LB_EN_LN0 = 1'b0 ; +parameter LB_EN_LN1 = 1'b0 ; +parameter LB_EN_LN2 = 1'b0 ; +parameter LB_EN_LN3 = 1'b0 ; +parameter LB_EN_LNCK = 1'b0 ; +parameter LB_POLAR_LN0 = 1'b0 ; +parameter LB_POLAR_LN1 = 1'b0 ; +parameter LB_POLAR_LN2 = 1'b0 ; +parameter LB_POLAR_LN3 = 1'b0 ; +parameter LB_POLAR_LNCK = 1'b0 ; +parameter LOW_LPRX_VTH = 1'b0 ; +parameter LPBK_DATA2TO1 = 4'b0000; +parameter LPBK_DATA2TO1_CK = 1'b0 ; +parameter LPBK_EN = 1'b0 ; +parameter LPBK_SEL = 4'b0000; +parameter LPBKTST_EN = 4'b0000; +parameter LPBKTST_EN_CK = 1'b0 ; +parameter LPRX_EN = 1'b1 ; +parameter LPRX_TST = 4'b0000; +parameter LPRX_TST_CK = 1'b0 ; +parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; +parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; +parameter LPTX_NIMP_LN0 = 3'b100 ; +parameter LPTX_NIMP_LN1 = 3'b100 ; +parameter LPTX_NIMP_LN2 = 3'b100 ; +parameter LPTX_NIMP_LN3 = 3'b100 ; +parameter LPTX_NIMP_LNCK = 3'b100 ; +parameter LPTX_PIMP_LN0 = 3'b100 ; +parameter LPTX_PIMP_LN1 = 3'b100 ; +parameter LPTX_PIMP_LN2 = 3'b100 ; +parameter LPTX_PIMP_LN3 = 3'b100 ; +parameter LPTX_PIMP_LNCK = 3'b100 ; +parameter MIPI_PMA_DIS_N = 1'b1 ; +parameter PGA_BIAS_LANE0 = 4'b1000 ; +parameter PGA_BIAS_LANE1 = 4'b1000 ; +parameter PGA_BIAS_LANE2 = 4'b1000 ; +parameter PGA_BIAS_LANE3 = 4'b1000 ; +parameter PGA_BIAS_LANECK = 4'b1000 ; +parameter PGA_GAIN_LANE0 = 4'b1000 ; +parameter PGA_GAIN_LANE1 = 4'b1000 ; +parameter PGA_GAIN_LANE2 = 4'b1000 ; +parameter PGA_GAIN_LANE3 = 4'b1000 ; +parameter PGA_GAIN_LANECK = 4'b1000 ; +parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; +parameter RX_ODT_TRIM_LANECK = 4'b1000 ; +parameter SLEWN_CTL_LN0 = 4'b1111 ; +parameter SLEWN_CTL_LN1 = 4'b1111 ; +parameter SLEWN_CTL_LN2 = 4'b1111 ; +parameter SLEWN_CTL_LN3 = 4'b1111 ; +parameter SLEWN_CTL_LNCK = 4'b1111 ; +parameter SLEWP_CTL_LN0 = 4'b1111 ; +parameter SLEWP_CTL_LN1 = 4'b1111 ; +parameter SLEWP_CTL_LN2 = 4'b1111 ; +parameter SLEWP_CTL_LN3 = 4'b1111 ; +parameter SLEWP_CTL_LNCK = 4'b1111 ; +parameter STP_UNIT = 2'b01 ; +parameter TERMN_CTL_LN0 = 4'b1000 ; +parameter TERMN_CTL_LN1 = 4'b1000 ; +parameter TERMN_CTL_LN2 = 4'b1000 ; +parameter TERMN_CTL_LN3 = 4'b1000 ; +parameter TERMN_CTL_LNCK = 4'b1000 ; +parameter TERMP_CTL_LN0 = 4'b1000 ; +parameter TERMP_CTL_LN1 = 4'b1000 ; +parameter TERMP_CTL_LN2 = 4'b1000 ; +parameter TERMP_CTL_LN3 = 4'b1000 ; +parameter TERMP_CTL_LNCK = 4'b1000 ; +parameter TEST_EN_LN0 = 1'b0 ; +parameter TEST_EN_LN1 = 1'b0 ; +parameter TEST_EN_LN2 = 1'b0 ; +parameter TEST_EN_LN3 = 1'b0 ; +parameter TEST_EN_LNCK = 1'b0 ; +parameter TEST_N_IMP_LN0 = 1'b0 ; +parameter TEST_N_IMP_LN1 = 1'b0 ; +parameter TEST_N_IMP_LN2 = 1'b0 ; +parameter TEST_N_IMP_LN3 = 1'b0 ; +parameter TEST_N_IMP_LNCK = 1'b0 ; +parameter TEST_P_IMP_LN0 = 1'b0 ; +parameter TEST_P_IMP_LN1 = 1'b0 ; +parameter TEST_P_IMP_LN2 = 1'b0 ; +parameter TEST_P_IMP_LN3 = 1'b0 ; +parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule module MIPI_CPHY(D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD, D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR, D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA, D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O @@ -2361,13 +2361,13 @@ output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD; output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD; output D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR; output [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA; -output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O; +output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O; output HSTX_FIFO_AE, HSTX_FIFO_AF; output HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR; output RX_CLK_MUXED; output TX_CLK_1X_O; output DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C; -output [7:0] MDRP_RDATA; +output [7:0] MDRP_RDATA; inout D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C; input D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN; input [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA; @@ -2381,110 +2381,110 @@ input MDRP_A_INC_I; input MDRP_CLK_I; input [1:0] MDRP_OPCODE_I; input PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX; -input ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; +input ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; input ARSTN_TX; -input RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; +input RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; input TX_CLK_1X_I; -input TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; -input TXHCLK_EN; +input TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; +input TXHCLK_EN; input DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2; input GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270; -input HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; +input HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; input HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2; -input LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; +input LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; input SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP; -parameter TX_PLLCLK = "NONE"; -parameter D0LN_HS_TX_EN = 1'b1; +parameter TX_PLLCLK = "NONE"; +parameter D0LN_HS_TX_EN = 1'b1; parameter D1LN_HS_TX_EN = 1'b1; parameter D2LN_HS_TX_EN = 1'b1; -parameter D0LN_HS_RX_EN = 1'b1; +parameter D0LN_HS_RX_EN = 1'b1; parameter D1LN_HS_RX_EN = 1'b1; parameter D2LN_HS_RX_EN = 1'b1; -parameter TX_HS_21BIT_MODE = 1'b0; -parameter RX_OUTCLK_SEL = 2'b00; -parameter TX_W_LENDIAN = 1'b1; -parameter CLK_SEL = 2'b00; -parameter LNDIV_RATIO = 4'b0000; -parameter LNDIV_EN = 1'b0; -parameter D0LN_TX_REASGN_A = 2'b00; -parameter D0LN_TX_REASGN_B = 2'b01; -parameter D0LN_TX_REASGN_C = 2'b10; -parameter D0LN_RX_HS_21BIT_MODE = 1'b0; -parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1; -parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001; -parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100; -parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1; -parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001; -parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100; -parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1; -parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001; -parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100; -parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0; -parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001; -parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100; -parameter D0LN_RX_W_LENDIAN = 1'b1; -parameter D0LN_RX_REASGN_A = 2'b00; -parameter D0LN_RX_REASGN_B = 2'b01; -parameter D0LN_RX_REASGN_C = 2'b10; -parameter HSRX_LNSEL = 3'b111; -parameter EQ_RS_LN0 = 3'b001; -parameter EQ_CS_LN0 = 3'b101; -parameter PGA_GAIN_LN0 = 4'b0110; -parameter PGA_BIAS_LN0 = 4'b1000; -parameter EQ_PBIAS_LN0 = 4'b0100; -parameter EQ_ZLD_LN0 = 4'b1000; -parameter D1LN_TX_REASGN_A = 2'b00; -parameter D1LN_TX_REASGN_B = 2'b01; -parameter D1LN_TX_REASGN_C = 2'b10; -parameter D1LN_RX_HS_21BIT_MODE = 1'b0; -parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1; -parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001; -parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100; -parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1; -parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001; -parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100; -parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1; -parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001; -parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100; -parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0; -parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001; -parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100; -parameter D1LN_RX_W_LENDIAN = 1'b1; -parameter D1LN_RX_REASGN_A = 2'b00; -parameter D1LN_RX_REASGN_B = 2'b01; -parameter D1LN_RX_REASGN_C = 2'b10; -parameter EQ_RS_LN1 = 3'b001; -parameter EQ_CS_LN1 = 3'b101; -parameter PGA_GAIN_LN1 = 4'b0110; -parameter PGA_BIAS_LN1 = 4'b1000; -parameter EQ_PBIAS_LN1 = 4'b0100; -parameter EQ_ZLD_LN1 = 4'b1000; -parameter D2LN_TX_REASGN_A = 2'b00; -parameter D2LN_TX_REASGN_B = 2'b01; -parameter D2LN_TX_REASGN_C = 2'b10; -parameter D2LN_RX_HS_21BIT_MODE = 1'b0; -parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1; -parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001; -parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100; -parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1; -parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001; -parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100; -parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1; -parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001; -parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100; -parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0; -parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001; -parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100; -parameter D2LN_RX_W_LENDIAN = 1'b1; -parameter D2LN_RX_REASGN_A = 2'b00; -parameter D2LN_RX_REASGN_B = 2'b01; -parameter D2LN_RX_REASGN_C = 2'b10; -parameter EQ_RS_LN2 = 3'b001; -parameter EQ_CS_LN2 = 3'b101; -parameter PGA_GAIN_LN2 = 4'b0110; -parameter PGA_BIAS_LN2 = 4'b1000; -parameter EQ_PBIAS_LN2 = 4'b0100; -parameter EQ_ZLD_LN2 = 4'b1000; +parameter TX_HS_21BIT_MODE = 1'b0; +parameter RX_OUTCLK_SEL = 2'b00; +parameter TX_W_LENDIAN = 1'b1; +parameter CLK_SEL = 2'b00; +parameter LNDIV_RATIO = 4'b0000; +parameter LNDIV_EN = 1'b0; +parameter D0LN_TX_REASGN_A = 2'b00; +parameter D0LN_TX_REASGN_B = 2'b01; +parameter D0LN_TX_REASGN_C = 2'b10; +parameter D0LN_RX_HS_21BIT_MODE = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D0LN_RX_W_LENDIAN = 1'b1; +parameter D0LN_RX_REASGN_A = 2'b00; +parameter D0LN_RX_REASGN_B = 2'b01; +parameter D0LN_RX_REASGN_C = 2'b10; +parameter HSRX_LNSEL = 3'b111; +parameter EQ_RS_LN0 = 3'b001; +parameter EQ_CS_LN0 = 3'b101; +parameter PGA_GAIN_LN0 = 4'b0110; +parameter PGA_BIAS_LN0 = 4'b1000; +parameter EQ_PBIAS_LN0 = 4'b0100; +parameter EQ_ZLD_LN0 = 4'b1000; +parameter D1LN_TX_REASGN_A = 2'b00; +parameter D1LN_TX_REASGN_B = 2'b01; +parameter D1LN_TX_REASGN_C = 2'b10; +parameter D1LN_RX_HS_21BIT_MODE = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D1LN_RX_W_LENDIAN = 1'b1; +parameter D1LN_RX_REASGN_A = 2'b00; +parameter D1LN_RX_REASGN_B = 2'b01; +parameter D1LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN1 = 3'b001; +parameter EQ_CS_LN1 = 3'b101; +parameter PGA_GAIN_LN1 = 4'b0110; +parameter PGA_BIAS_LN1 = 4'b1000; +parameter EQ_PBIAS_LN1 = 4'b0100; +parameter EQ_ZLD_LN1 = 4'b1000; +parameter D2LN_TX_REASGN_A = 2'b00; +parameter D2LN_TX_REASGN_B = 2'b01; +parameter D2LN_TX_REASGN_C = 2'b10; +parameter D2LN_RX_HS_21BIT_MODE = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D2LN_RX_W_LENDIAN = 1'b1; +parameter D2LN_RX_REASGN_A = 2'b00; +parameter D2LN_RX_REASGN_B = 2'b01; +parameter D2LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN2 = 3'b001; +parameter EQ_CS_LN2 = 3'b101; +parameter PGA_GAIN_LN2 = 4'b0110; +parameter PGA_BIAS_LN2 = 4'b1000; +parameter EQ_PBIAS_LN2 = 4'b0100; +parameter EQ_ZLD_LN2 = 4'b1000; endmodule module GTR12_QUAD(); @@ -2517,13 +2517,13 @@ input [2:0] RCLKSEL; input [7:0] DLLSTEP; input [7:0] WSTEP; input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD; -output DQSR90, DQSW0, DQSW270; +output DQSR90, DQSW0, DQSW270; output [2:0] RPOINT, WPOINT; output RVALID,RBURST, RFLAG, WFLAG; -parameter FIFO_MODE_SEL = 1'b0; -parameter RD_PNTR = 3'b000; -parameter DQS_MODE = "X1"; -parameter HWL = "false"; +parameter FIFO_MODE_SEL = 1'b0; +parameter RD_PNTR = 3'b000; +parameter DQS_MODE = "X1"; +parameter HWL = "false"; endmodule // Added form adc.v diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg index 7e4c3ace2..09fee1953 100644 --- a/techlibs/ice40/ice40_dsp.pmg +++ b/techlibs/ice40/ice40_dsp.pmg @@ -33,7 +33,7 @@ code sigA sigB sigH return sig.extract(0, i); }; auto unextend_unsigned = [](const SigSpec &sig) { - int i; + int i; for (i = GetSize(sig)-1; i > 0; i--) if (sig[i] != SigBit(State::S0)) break; @@ -61,7 +61,7 @@ code sigA sigB sigH if (i == 0) reject; - for (int j = 0, wire_width = 0; j <= i; j++) + for (int j = 0, wire_width = 0; j <= i; j++) if (nusers(O[j]) == 0) wire_width++; else { diff --git a/techlibs/intel_alm/common/abc9_map.v b/techlibs/intel_alm/common/abc9_map.v index 9d11bb240..a0969d44d 100644 --- a/techlibs/intel_alm/common/abc9_map.v +++ b/techlibs/intel_alm/common/abc9_map.v @@ -1,5 +1,5 @@ -// This file exists to map purely-synchronous flops to ABC9 flops, while -// mapping flops with asynchronous-clear as boxes, this is because ABC9 +// This file exists to map purely-synchronous flops to ABC9 flops, while +// mapping flops with asynchronous-clear as boxes, this is because ABC9 // doesn't support asynchronous-clear flops in sequential synthesis. module MISTRAL_FF( diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v index d4ed95173..d525cafd9 100644 --- a/techlibs/intel_alm/common/megafunction_bb.v +++ b/techlibs/intel_alm/common/megafunction_bb.v @@ -12,81 +12,81 @@ module altera_pll parameter operation_mode = "internal feedback", parameter deserialization_factor = 4, parameter data_rate = 0, - + parameter sim_additional_refclk_cycles_to_lock = 0, parameter output_clock_frequency0 = "0 ps", parameter phase_shift0 = "0 ps", parameter duty_cycle0 = 50, - + parameter output_clock_frequency1 = "0 ps", parameter phase_shift1 = "0 ps", parameter duty_cycle1 = 50, - + parameter output_clock_frequency2 = "0 ps", parameter phase_shift2 = "0 ps", parameter duty_cycle2 = 50, - + parameter output_clock_frequency3 = "0 ps", parameter phase_shift3 = "0 ps", parameter duty_cycle3 = 50, - + parameter output_clock_frequency4 = "0 ps", parameter phase_shift4 = "0 ps", parameter duty_cycle4 = 50, - + parameter output_clock_frequency5 = "0 ps", parameter phase_shift5 = "0 ps", parameter duty_cycle5 = 50, - + parameter output_clock_frequency6 = "0 ps", parameter phase_shift6 = "0 ps", parameter duty_cycle6 = 50, - + parameter output_clock_frequency7 = "0 ps", parameter phase_shift7 = "0 ps", parameter duty_cycle7 = 50, - + parameter output_clock_frequency8 = "0 ps", parameter phase_shift8 = "0 ps", parameter duty_cycle8 = 50, - + parameter output_clock_frequency9 = "0 ps", parameter phase_shift9 = "0 ps", - parameter duty_cycle9 = 50, + parameter duty_cycle9 = 50, + - parameter output_clock_frequency10 = "0 ps", parameter phase_shift10 = "0 ps", parameter duty_cycle10 = 50, - + parameter output_clock_frequency11 = "0 ps", parameter phase_shift11 = "0 ps", parameter duty_cycle11 = 50, - + parameter output_clock_frequency12 = "0 ps", parameter phase_shift12 = "0 ps", parameter duty_cycle12 = 50, - + parameter output_clock_frequency13 = "0 ps", parameter phase_shift13 = "0 ps", parameter duty_cycle13 = 50, - + parameter output_clock_frequency14 = "0 ps", parameter phase_shift14 = "0 ps", parameter duty_cycle14 = 50, - + parameter output_clock_frequency15 = "0 ps", parameter phase_shift15 = "0 ps", parameter duty_cycle15 = 50, - + parameter output_clock_frequency16 = "0 ps", parameter phase_shift16 = "0 ps", parameter duty_cycle16 = 50, - + parameter output_clock_frequency17 = "0 ps", parameter phase_shift17 = "0 ps", parameter duty_cycle17 = 50, - + parameter clock_name_0 = "", parameter clock_name_1 = "", parameter clock_name_2 = "", @@ -115,126 +115,126 @@ module altera_pll parameter n_cnt_lo_div = 1, parameter n_cnt_bypass_en = "false", parameter n_cnt_odd_div_duty_en = "false", - parameter c_cnt_hi_div0 = 1, + parameter c_cnt_hi_div0 = 1, parameter c_cnt_lo_div0 = 1, parameter c_cnt_bypass_en0 = "false", parameter c_cnt_in_src0 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en0 = "false", parameter c_cnt_prst0 = 1, parameter c_cnt_ph_mux_prst0 = 0, - parameter c_cnt_hi_div1 = 1, + parameter c_cnt_hi_div1 = 1, parameter c_cnt_lo_div1 = 1, parameter c_cnt_bypass_en1 = "false", parameter c_cnt_in_src1 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en1 = "false", parameter c_cnt_prst1 = 1, parameter c_cnt_ph_mux_prst1 = 0, - parameter c_cnt_hi_div2 = 1, + parameter c_cnt_hi_div2 = 1, parameter c_cnt_lo_div2 = 1, parameter c_cnt_bypass_en2 = "false", parameter c_cnt_in_src2 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en2 = "false", parameter c_cnt_prst2 = 1, parameter c_cnt_ph_mux_prst2 = 0, - parameter c_cnt_hi_div3 = 1, + parameter c_cnt_hi_div3 = 1, parameter c_cnt_lo_div3 = 1, parameter c_cnt_bypass_en3 = "false", parameter c_cnt_in_src3 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en3 = "false", parameter c_cnt_prst3 = 1, parameter c_cnt_ph_mux_prst3 = 0, - parameter c_cnt_hi_div4 = 1, + parameter c_cnt_hi_div4 = 1, parameter c_cnt_lo_div4 = 1, parameter c_cnt_bypass_en4 = "false", parameter c_cnt_in_src4 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en4 = "false", parameter c_cnt_prst4 = 1, parameter c_cnt_ph_mux_prst4 = 0, - parameter c_cnt_hi_div5 = 1, + parameter c_cnt_hi_div5 = 1, parameter c_cnt_lo_div5 = 1, parameter c_cnt_bypass_en5 = "false", parameter c_cnt_in_src5 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en5 = "false", parameter c_cnt_prst5 = 1, parameter c_cnt_ph_mux_prst5 = 0, - parameter c_cnt_hi_div6 = 1, + parameter c_cnt_hi_div6 = 1, parameter c_cnt_lo_div6 = 1, parameter c_cnt_bypass_en6 = "false", parameter c_cnt_in_src6 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en6 = "false", parameter c_cnt_prst6 = 1, parameter c_cnt_ph_mux_prst6 = 0, - parameter c_cnt_hi_div7 = 1, + parameter c_cnt_hi_div7 = 1, parameter c_cnt_lo_div7 = 1, parameter c_cnt_bypass_en7 = "false", parameter c_cnt_in_src7 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en7 = "false", parameter c_cnt_prst7 = 1, parameter c_cnt_ph_mux_prst7 = 0, - parameter c_cnt_hi_div8 = 1, + parameter c_cnt_hi_div8 = 1, parameter c_cnt_lo_div8 = 1, parameter c_cnt_bypass_en8 = "false", parameter c_cnt_in_src8 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en8 = "false", parameter c_cnt_prst8 = 1, parameter c_cnt_ph_mux_prst8 = 0, - parameter c_cnt_hi_div9 = 1, + parameter c_cnt_hi_div9 = 1, parameter c_cnt_lo_div9 = 1, parameter c_cnt_bypass_en9 = "false", parameter c_cnt_in_src9 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en9 = "false", parameter c_cnt_prst9 = 1, parameter c_cnt_ph_mux_prst9 = 0, - parameter c_cnt_hi_div10 = 1, + parameter c_cnt_hi_div10 = 1, parameter c_cnt_lo_div10 = 1, parameter c_cnt_bypass_en10 = "false", parameter c_cnt_in_src10 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en10 = "false", parameter c_cnt_prst10 = 1, parameter c_cnt_ph_mux_prst10 = 0, - parameter c_cnt_hi_div11 = 1, + parameter c_cnt_hi_div11 = 1, parameter c_cnt_lo_div11 = 1, parameter c_cnt_bypass_en11 = "false", parameter c_cnt_in_src11 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en11 = "false", parameter c_cnt_prst11 = 1, parameter c_cnt_ph_mux_prst11 = 0, - parameter c_cnt_hi_div12 = 1, + parameter c_cnt_hi_div12 = 1, parameter c_cnt_lo_div12 = 1, parameter c_cnt_bypass_en12 = "false", parameter c_cnt_in_src12 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en12 = "false", parameter c_cnt_prst12 = 1, parameter c_cnt_ph_mux_prst12 = 0, - parameter c_cnt_hi_div13 = 1, + parameter c_cnt_hi_div13 = 1, parameter c_cnt_lo_div13 = 1, parameter c_cnt_bypass_en13 = "false", parameter c_cnt_in_src13 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en13 = "false", parameter c_cnt_prst13 = 1, parameter c_cnt_ph_mux_prst13 = 0, - parameter c_cnt_hi_div14 = 1, + parameter c_cnt_hi_div14 = 1, parameter c_cnt_lo_div14 = 1, parameter c_cnt_bypass_en14 = "false", parameter c_cnt_in_src14 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en14 = "false", parameter c_cnt_prst14 = 1, parameter c_cnt_ph_mux_prst14 = 0, - parameter c_cnt_hi_div15 = 1, + parameter c_cnt_hi_div15 = 1, parameter c_cnt_lo_div15 = 1, parameter c_cnt_bypass_en15 = "false", parameter c_cnt_in_src15 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en15 = "false", parameter c_cnt_prst15 = 1, parameter c_cnt_ph_mux_prst15 = 0, - parameter c_cnt_hi_div16 = 1, + parameter c_cnt_hi_div16 = 1, parameter c_cnt_lo_div16 = 1, parameter c_cnt_bypass_en16 = "false", parameter c_cnt_in_src16 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en16 = "false", parameter c_cnt_prst16 = 1, parameter c_cnt_ph_mux_prst16 = 0, - parameter c_cnt_hi_div17 = 1, + parameter c_cnt_hi_div17 = 1, parameter c_cnt_lo_div17 = 1, parameter c_cnt_bypass_en17 = "false", parameter c_cnt_in_src17 = "ph_mux_clk", @@ -260,9 +260,9 @@ module altera_pll parameter pll_clkin_1_src = "clk_0", parameter pll_clk_loss_sw_en = "false", parameter pll_auto_clk_sw_en = "false", - parameter pll_manu_clk_sw_en = "false", + parameter pll_manu_clk_sw_en = "false", parameter pll_clk_sw_dly = 0, - parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", + parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss" ) ( //input @@ -279,7 +279,7 @@ module altera_pll input extswitch, input adjpllin, input cclk, - + //output output [ number_of_clocks -1 : 0] outclk, output fboutclk, diff --git a/techlibs/lattice/cells_sim_nexus.v b/techlibs/lattice/cells_sim_nexus.v index d1c8bf0d7..49111a7ad 100644 --- a/techlibs/lattice/cells_sim_nexus.v +++ b/techlibs/lattice/cells_sim_nexus.v @@ -446,7 +446,7 @@ module OXIDE_DSP_SIM #( input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT, output wire [Z_WIDTH-1:0] Z ); - + localparam M_WIDTH = (A_WIDTH+B_WIDTH); /******** REGISTERS ********/ @@ -511,7 +511,7 @@ module OXIDE_DSP_SIM #( if (ADDSUB_USED) begin assign pipe_d = mult_m; assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q}; - assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext); + assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext); end else begin assign z_d = mult_m; end diff --git a/techlibs/lattice/dsp_map_nexus.v b/techlibs/lattice/dsp_map_nexus.v index 61d2d96a8..a2ee71a21 100644 --- a/techlibs/lattice/dsp_map_nexus.v +++ b/techlibs/lattice/dsp_map_nexus.v @@ -94,10 +94,10 @@ module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [ .REGINPUTC("BYPASS"), .REGOUTPUT("BYPASS") ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), + .A(A), + .B(B), .C({6'b0, C}), - .SIGNED(A_SIGNED ? 1'b1 : 1'b0), + .SIGNED(A_SIGNED ? 1'b1 : 1'b0), .ADDSUB(SUBTRACT ? 1'b1 : 1'b0), .Z(Y) ); diff --git a/techlibs/lattice/lattice_dsp_nexus.cc b/techlibs/lattice/lattice_dsp_nexus.cc index 083af2595..442182f22 100644 --- a/techlibs/lattice/lattice_dsp_nexus.cc +++ b/techlibs/lattice/lattice_dsp_nexus.cc @@ -25,8 +25,8 @@ struct LatticeDspNexusPass : public Pass { for (auto module : design->selected_modules()) { lattice_dsp_nexus_pm pm(module, module->cells()); - - pm.run_nexus_mac9_4lane(); + + pm.run_nexus_mac9_4lane(); pm.run_nexus_mac18(); pm.run_nexus_preadd18(); } diff --git a/techlibs/lattice/lattice_dsp_nexus.pmg b/techlibs/lattice/lattice_dsp_nexus.pmg index 8c16891b1..2ad38840b 100644 --- a/techlibs/lattice/lattice_dsp_nexus.pmg +++ b/techlibs/lattice/lattice_dsp_nexus.pmg @@ -38,7 +38,7 @@ code mac->setPort(\B, port(mul, \B)); mac->setPort(\C, port(add, add_C)); mac->setPort(\Y, port(add, \Y)); - mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED)); + mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED)); mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0); autoremove(mul); @@ -178,9 +178,9 @@ code { Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE"); - - auto ext9 = [&](SigSpec s) { - s.extend_u0(9, is_signed); + + auto ext9 = [&](SigSpec s) { + s.extend_u0(9, is_signed); return s; }; diff --git a/techlibs/lattice/lattice_gsr.cc b/techlibs/lattice/lattice_gsr.cc index a60b54b16..f7d40c056 100644 --- a/techlibs/lattice/lattice_gsr.cc +++ b/techlibs/lattice/lattice_gsr.cc @@ -83,12 +83,12 @@ struct LatticeGsrPass : public Pass { { if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO") continue; - + bool gsren = found_gsr; if (cell->get_bool_attribute(ID(nogsr))) gsren = false; cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED")); - + } if (!found_gsr) diff --git a/techlibs/microchip/LSRAM.txt b/techlibs/microchip/LSRAM.txt index 9c22e4f30..3668c1b71 100644 --- a/techlibs/microchip/LSRAM.txt +++ b/techlibs/microchip/LSRAM.txt @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -28,9 +28,9 @@ ram block $__LSRAM_TDP_ { init any; # port A and port B are allowed to have different widths, but they MUST have - # WIDTH values of the same set. + # WIDTH values of the same set. # Example: Port A has a Data Width of 1. Then Port B's Data Width must be either - # 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set). + # 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set). # WIDTH_1 = {1, 2, 4, 8, 16} # WIDTH_2 = {5, 10, 20} @@ -38,7 +38,7 @@ ram block $__LSRAM_TDP_ { # "byte" must be larger than width, or width must be a multipler of "byte" # if "byte" > WIDTH, a single enable wire is inferred # otherwise, WIDTH/byte number of enable wires are inferred - # + # # WIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire # WIDTH = {16, 20} requires 2 enable wire @@ -58,7 +58,7 @@ ram block $__LSRAM_TDP_ { byte 8; } option "WIDTH_CONFIG" "ALIGN" { - + # Data-Width| Address bits # 5 | 12 # 10 | 11 @@ -72,14 +72,14 @@ ram block $__LSRAM_TDP_ { widths 5 10 20 per_port; byte 10; } - - + + port srsw "A" "B" { # read & write width must be same width tied; - + # clock polarity is rising clock posedge; @@ -101,8 +101,8 @@ ram block $__LSRAM_TDP_ { rdwr no_change; # Write transparency: - # For write ports, define behaviour when another synchronous read port - # reads from the same memory cell that said write port is writing to at the same time. + # For write ports, define behaviour when another synchronous read port + # reads from the same memory cell that said write port is writing to at the same time. wrtrans all old; } portoption "WRITE_MODE" "WRITE_FIRST" { @@ -123,9 +123,9 @@ ram block $__LSRAM_TDP_ { # two-port configuration ram block $__LSRAM_SDP_ { - + # since two-port configuration is dedicated for wide-read/write, - # we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs + # we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs # inplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should # be less than 2 TDP. cost 129; @@ -147,10 +147,10 @@ ram block $__LSRAM_SDP_ { # width = 32, byte-write size is 8, ignore other widths byte 8; - + } option "WIDTH_CONFIG" "ALIGN" { - + # Data-Width| Address bits # 5 | 12 # 10 | 11 @@ -166,7 +166,7 @@ ram block $__LSRAM_SDP_ { port sw "W" { # only consider wide write - + option "WIDTH_CONFIG" "REGULAR" width 32; option "WIDTH_CONFIG" "ALIGN" width 40; @@ -174,7 +174,7 @@ ram block $__LSRAM_SDP_ { # only simple write supported for two-port mode wrtrans all old; - + optional; } port sr "R" { diff --git a/techlibs/microchip/LSRAM_map.v b/techlibs/microchip/LSRAM_map.v index c84b5dd19..cfe765a1a 100644 --- a/techlibs/microchip/LSRAM_map.v +++ b/techlibs/microchip/LSRAM_map.v @@ -71,7 +71,7 @@ parameter PORT_A_WR_USED = 0; wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000; wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000; -// wires for write data +// wires for write data generate wire [19:0] A_write_data; wire [19:0] B_write_data; @@ -115,9 +115,9 @@ wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 : (PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100; // write modes -wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : +wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10; -wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : +wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10; RAM1K20 #( @@ -155,7 +155,7 @@ RAM1K20 #( .B_DOUT_ARST_N(1'b1), // Disable ECC for TDP - .ECC_EN(1'b0), + .ECC_EN(1'b0), .ECC_BYPASS(1'b1), .BUSY_FB(1'b0) @@ -212,7 +212,7 @@ generate wire [1:0] A_write_EN; wire [1:0] B_write_EN; - // write port (A provides MSB) + // write port (A provides MSB) if (PORT_W_WIDTH == 32) begin assign B_write_data[3:0] = PORT_W_WR_DATA[3:0]; @@ -232,7 +232,7 @@ generate assign A_write_data[9] = 1'b0; assign A_write_data[14] = 1'b0; assign A_write_data[19] = 1'b0; - + end else if (PORT_W_WIDTH == 40) begin assign B_write_data = PORT_W_WR_DATA[19:0]; assign A_write_data = PORT_W_WR_DATA[39:20]; @@ -265,7 +265,7 @@ endgenerate wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 : (PORT_R_WIDTH == 2) ? 3'b001 : (PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 : - (PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : + (PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : (PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101; wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 : (PORT_W_WIDTH == 2) ? 3'b001 : @@ -311,7 +311,7 @@ RAM1K20 #( .B_DOUT_ARST_N(1'b1), // Disable ECC for SDP - .ECC_EN(1'b0), + .ECC_EN(1'b0), .ECC_BYPASS(1'b1), .BUSY_FB(1'b0) ); diff --git a/techlibs/microchip/arith_map.v b/techlibs/microchip/arith_map.v index 3eb2e2f2c..7e77de218 100644 --- a/techlibs/microchip/arith_map.v +++ b/techlibs/microchip/arith_map.v @@ -48,7 +48,7 @@ module \$__microchip_XOR8_ (A, Y); XOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y)); - + endmodule (* techmap_celltype = "$alu" *) diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v index 6fc3094b2..6d5e09be4 100644 --- a/techlibs/microchip/cells_sim.v +++ b/techlibs/microchip/cells_sim.v @@ -155,7 +155,7 @@ endmodule // sequential elements -// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow +// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow // see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html (* abc9_flop, lib_whitebox *) @@ -196,7 +196,7 @@ module MICROCHIP_SYNC_RESET_DFF( always @(posedge CLK) begin if (En == 1) begin - if (Reset == 0) + if (Reset == 0) Q <= 0; else Q <= D; @@ -258,7 +258,7 @@ module ARI1 ( (* abc9_carry *) output FCO, - input A, B, C, D, + input A, B, C, D, output Y, S ); parameter [19:0] INIT = 20'h0; @@ -271,9 +271,9 @@ module ARI1 ( wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17]; wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0); assign FCO = P ? FCI : G; - + specify - //pin to pin path delay + //pin to pin path delay (A => Y ) = 472; (B => Y ) = 407; (C => Y ) = 238; @@ -647,7 +647,7 @@ module RAM1K20 ( input B_DOUT_EN, input B_DOUT_SRST_N, input B_DOUT_ARST_N, - input ECC_EN, + input ECC_EN, input ECC_BYPASS, output SB_CORRECT, output DB_DETECT, @@ -684,7 +684,7 @@ module RAM64x12 ( input R_ADDR_EN, input R_ADDR_SL_N, input R_ADDR_SD, - input R_ADDR_AL_N, + input R_ADDR_AL_N, input R_ADDR_AD_N, input BLK_EN, output [11:0] R_DATA, diff --git a/techlibs/microchip/microchip_dsp.pmg b/techlibs/microchip/microchip_dsp.pmg index 2573135ee..4141d9961 100644 --- a/techlibs/microchip/microchip_dsp.pmg +++ b/techlibs/microchip/microchip_dsp.pmg @@ -1,7 +1,7 @@ // ISC License -// +// // Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. @@ -16,12 +16,12 @@ // This file describes the main pattern matcher setup (of three total) that -// forms the `microchip_dsp` pass described in microchip_dsp.cc +// forms the `microchip_dsp` pass described in microchip_dsp.cc // At a high level, it works as follows: // ( 1) Starting from a DSP cell. Capture DSP configurations as states // ( 2) Match for pre-adder // ( 3) Match for post-adder -// ( 4) Match register 'A', 'B', 'D', 'P' +// ( 4) Match register 'A', 'B', 'D', 'P' // ( 5) If post-adder and PREG both present, check if PREG feeds into post-adder. // This indicates an accumulator situation like the ASCII diagram below: // +--------------------------------+ @@ -110,21 +110,21 @@ code bypassA bypassB bypassC bypassD bypassPASUB bypassP endcode // (2) Match for pre-adder -// +// code sigA sigB sigD preAdderStatic moveBtoA subpattern(preAddMatching); preAdderStatic = u_preAdderStatic; moveBtoA = false; if (preAdderStatic) { - + if (port(preAdderStatic, \Y) == sigA) { //used for packing moveBtoA = true; - // sigA should be the input to the multiplier without the preAdd. sigB and sigD should be - //the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then + // sigA should be the input to the multiplier without the preAdd. sigB and sigD should be + //the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then // we basically swap it. sigA = sigB; } @@ -144,7 +144,7 @@ code postAdderStatic sigP sigC if (postAdderStatic) { //sigC will be whichever input to the postAdder that is NOT from the multiplier - // u_postAddAB is the input to the postAdder from the multiplier + // u_postAddAB is the input to the postAdder from the multiplier sigC = port(postAdderStatic, u_postAddAB == \A ? \B : \A); sigP = port(postAdderStatic, \Y); } @@ -269,7 +269,7 @@ code if (postAdd) { if (postAdd->type.in($sub) && postAddAB == \A) { - // if $sub, the multiplier output must match to $sub.B, otherwise no match + // if $sub, the multiplier output must match to $sub.B, otherwise no match } else { u_postAddAB = postAddAB; u_postAdderStatic = postAdd; @@ -286,11 +286,11 @@ endcode subpattern preAddMatching arg sigA sigB sigD bypassB bypassD bypassPASUB -code +code u_preAdderStatic = nullptr; // Ensure that preAdder not already used - // Assume we can inspect port D to see if its all zeros. + // Assume we can inspect port D to see if its all zeros. if (!(sigD.empty() || sigD.is_fully_zero())) reject; if (!bypassB.is_fully_ones()) reject; if (!bypassD.is_fully_ones()) reject; diff --git a/techlibs/microchip/microchip_dsp_CREG.pmg b/techlibs/microchip/microchip_dsp_CREG.pmg index d1b15d460..a89c0a858 100644 --- a/techlibs/microchip/microchip_dsp_CREG.pmg +++ b/techlibs/microchip/microchip_dsp_CREG.pmg @@ -1,7 +1,7 @@ // ISC License -// +// // Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. @@ -164,5 +164,5 @@ code argQ argQ = Q; dffD.replace(argQ, D); } - + endcode diff --git a/techlibs/microchip/microchip_dsp_cascade.pmg b/techlibs/microchip/microchip_dsp_cascade.pmg index d26fdf784..b3d8ea7dc 100644 --- a/techlibs/microchip/microchip_dsp_cascade.pmg +++ b/techlibs/microchip/microchip_dsp_cascade.pmg @@ -1,7 +1,7 @@ // ISC License -// +// // Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. @@ -18,10 +18,10 @@ // This file describes the third of three pattern matcher setups that // forms the `microchip_dsp` pass described in microchip_dsp.cc // At a high level, it works as follows: -// (1) Starting from a DSP cell that +// (1) Starting from a DSP cell that // (a) CDIN_FDBK_SEL is set to default "00" // (b) doesn't already use the 'PCOUT' port -// (2) Match another DSP cell that +// (2) Match another DSP cell that // (a) does not have the CREG enabled, // (b) 'C' port is driven by the 'P' output of the previous DSP cell // (c) has its 'PCIN' port unused @@ -72,7 +72,7 @@ code }; endcode -// (1) Starting from a DSP cell that +// (1) Starting from a DSP cell that // (a) CDIN_FDBK_SEL is set to default "00" // (b) doesn't already use the 'PCOUT' port match first @@ -133,7 +133,7 @@ finally { dsp_pcin->setPort(\ARSHFT17, State::S1); } - + log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin); @@ -154,7 +154,7 @@ subpattern tail arg first arg next -// (2) Match another DSP cell that +// (2) Match another DSP cell that // (a) does not have the CREG enabled, // (b) 'C' port is driven by the 'P' output of the previous DSP cell // (c) has its 'PCIN' port unused @@ -213,7 +213,7 @@ code chain.emplace_back(next, shift); visited.insert(next); - + SigSpec sigC = unextend(port(next, \C)); // Make sure driverDSP.P === DSP.C @@ -231,6 +231,6 @@ finally visited.erase(next); chain.pop_back(); } - + endcode diff --git a/techlibs/microchip/polarfire_dsp_map.v b/techlibs/microchip/polarfire_dsp_map.v index b416841fb..b0cb50d07 100644 --- a/techlibs/microchip/polarfire_dsp_map.v +++ b/techlibs/microchip/polarfire_dsp_map.v @@ -27,9 +27,9 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); // For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide: // https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf MACC_PA _TECHMAP_REPLACE_ ( - .DOTP(1'b0), - .SIMD(1'b0), - .OVFL_CARRYOUT_SEL(1'b0), + .DOTP(1'b0), + .SIMD(1'b0), + .OVFL_CARRYOUT_SEL(1'b0), .AL_N(1'b1), .A(A), @@ -47,7 +47,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D_ARST_N(1'b1), .D_SRST_N(1'b1), .D_EN(1'b1), - + .CARRYIN(1'b0), .C(48'b0), .C_BYPASS(1'b1), @@ -55,7 +55,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .C_SRST_N(1'b1), .C_EN(1'b1), - + .P(P_48), .P_BYPASS(1'b1), diff --git a/techlibs/microchip/uSRAM.txt b/techlibs/microchip/uSRAM.txt index 10f9a1435..8da9c52ed 100644 --- a/techlibs/microchip/uSRAM.txt +++ b/techlibs/microchip/uSRAM.txt @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -30,10 +30,10 @@ ram block $__uSRAM_AR_ { port sw "W" { clock posedge; - # collision not supported, but write takes precedence and read data is invalid while writing to + # collision not supported, but write takes precedence and read data is invalid while writing to # the same address wrtrans all new; - + optional; } port ar "R" { @@ -57,7 +57,7 @@ widths 12 per_port; # collision not supported wrtrans all new; - + optional; } port sr "R" { diff --git a/techlibs/microchip/uSRAM_map.v b/techlibs/microchip/uSRAM_map.v index 81c76f0f1..8fafb1ece 100644 --- a/techlibs/microchip/uSRAM_map.v +++ b/techlibs/microchip/uSRAM_map.v @@ -48,7 +48,7 @@ RAM64x12 #( .R_ADDR_EN(1'b0), .R_ADDR_SL_N(1'b1), .R_ADDR_SD(1'b0), - .R_ADDR_AL_N(1'b1), + .R_ADDR_AL_N(1'b1), .R_ADDR_AD_N(1'b0), .BLK_EN(PORT_R_USED ? 1'b1 : 1'b0), .R_DATA(PORT_R_RD_DATA), @@ -103,7 +103,7 @@ RAM64x12 #( .R_ADDR_EN(PORT_R_RD_EN), .R_ADDR_SL_N(1'b1), .R_ADDR_SD(1'b0), - .R_ADDR_AL_N(1'b1), + .R_ADDR_AL_N(1'b1), .R_ADDR_AD_N(1'b0), .BLK_EN(PORT_R_USED ? 1'b1 : 1'b0), .R_DATA(PORT_R_RD_DATA), diff --git a/techlibs/nanoxplore/brams_init.vh b/techlibs/nanoxplore/brams_init.vh index b93839c5a..8df808d88 100644 --- a/techlibs/nanoxplore/brams_init.vh +++ b/techlibs/nanoxplore/brams_init.vh @@ -3,7 +3,7 @@ function [409600-1:0] bram_init_to_string; input integer blocks; input integer width; reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas - reg [24-1:0] temp2; + reg [24-1:0] temp2; integer i; integer j; begin diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index e11aaabee..1c83fb2c0 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -172,15 +172,15 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 end wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 }; - wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28, - O27, O26, O25, O24, O23, O22, O21, O20, O19, + wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28, + O27, O26, O25, O24, O23, O22, O21, O20, O19, O18, O17, O16, O15, O14, O13, O12, O11, O10, O9, O8, O7, O6, O5, O4, O3, O2, O1 }; wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28, I27, I26, I25, I24, I23, I22, I21, I20, I19, I18, I17, I16, I15, I14, I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1 }; - generate + generate if (mode==0) begin assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }]; end @@ -196,7 +196,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 else if (mode==4) begin assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] }; end - else + else $error("Unknown NX_RFB_U mode"); endgenerate diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index 6e6a96035..cb0405052 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -52,7 +52,7 @@ static void nx_carry_chain(Module *module) { if (cell->type == ID(NX_CY_1BIT)) { if (cell->getParam(ID(first)).as_int() == 0) continue; - + vector chain; Cell *current = cell; chain.push_back(current); @@ -124,8 +124,8 @@ static void nx_carry_chain(Module *module) } cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A)))); cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B)))); - - if (c.second.at(i)->hasPort(ID(S))) + + if (c.second.at(i)->hasPort(ID(S))) cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S))); j = (j + 1) % 4; @@ -148,7 +148,7 @@ struct NXCarryPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing NX_CARRY pass.\n"); - + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/techlibs/nanoxplore/rf_rams_map_l.v b/techlibs/nanoxplore/rf_rams_map_l.v index e529ce1e1..d712a8572 100644 --- a/techlibs/nanoxplore/rf_rams_map_l.v +++ b/techlibs/nanoxplore/rf_rams_map_l.v @@ -2,7 +2,7 @@ module $__NX_RFB_L_ ( input PORT_W_CLK, input PORT_W_WR_EN, input [5:0] PORT_W_ADDR, - input [15:0] PORT_W_WR_DATA, + input [15:0] PORT_W_WR_DATA, input PORT_R_CLK, input PORT_R_RD_EN, input [5:0] PORT_R_ADDR, diff --git a/techlibs/nanoxplore/rf_rams_map_m.v b/techlibs/nanoxplore/rf_rams_map_m.v index a64dc3388..053797a43 100644 --- a/techlibs/nanoxplore/rf_rams_map_m.v +++ b/techlibs/nanoxplore/rf_rams_map_m.v @@ -2,7 +2,7 @@ module $__NX_RFB_M_ ( input PORT_W_CLK, input PORT_W_WR_EN, input [5:0] PORT_W_ADDR, - input [15:0] PORT_W_WR_DATA, + input [15:0] PORT_W_WR_DATA, input PORT_R_CLK, input PORT_R_RD_EN, input [5:0] PORT_R_ADDR, diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 0b87c98c7..525985677 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -1,8 +1,8 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2024 Hannah Ravensloft - * Copyright (C) 2024 Miodrag Milanovic + * Copyright (C) 2024 Hannah Ravensloft + * Copyright (C) 2024 Miodrag Milanovic * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -217,7 +217,7 @@ struct SynthNanoXplorePass : public ScriptPass postfix = "_m"; } else if (family == "large") { postfix = "_l"; - } else + } else log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family); if (!design->full_selection()) diff --git a/techlibs/quicklogic/pp3/abc9_map.v b/techlibs/quicklogic/pp3/abc9_map.v index 46c11d675..42434a3af 100644 --- a/techlibs/quicklogic/pp3/abc9_map.v +++ b/techlibs/quicklogic/pp3/abc9_map.v @@ -1,5 +1,5 @@ -// This file exists to map purely-synchronous flops to ABC9 flops, while -// mapping flops with asynchronous-set/clear as boxes, this is because ABC9 +// This file exists to map purely-synchronous flops to ABC9 flops, while +// mapping flops with asynchronous-set/clear as boxes, this is because ABC9 // doesn't support asynchronous-set/clear flops in sequential synthesis. module dffepc ( diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc index eeb06060e..c2fbed4fd 100644 --- a/techlibs/quicklogic/ql_bram_merge.cc +++ b/techlibs/quicklogic/ql_bram_merge.cc @@ -180,7 +180,7 @@ struct QlBramMergeWorker { }; struct QlBramMergePass : public Pass { - + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} void help() override diff --git a/techlibs/quicklogic/ql_bram_types.cc b/techlibs/quicklogic/ql_bram_types.cc index 5e423b18d..fda90b203 100644 --- a/techlibs/quicklogic/ql_bram_types.cc +++ b/techlibs/quicklogic/ql_bram_types.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct QlBramTypesPass : public Pass { - + QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {} void help() override @@ -81,7 +81,7 @@ struct QlBramTypesPass : public Pass { { if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS))) continue; - + RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS)); bool split = mode_bits.extract(80).as_bool(); @@ -139,7 +139,7 @@ struct QlBramTypesPass : public Pass { type += "SYNC_"; else type += "ASYNC_"; - } else + } else type += "_BRAM_"; if (split) { diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v index 0035deccf..f2b8113d1 100644 --- a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -15,7 +15,7 @@ // SPDX-License-Identifier: Apache-2.0 module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA, - PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA); + PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA); parameter INIT = 0; diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index e65be1c58..23997fc02 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -342,7 +342,7 @@ struct SynthQuickLogicPass : public ScriptPass { run("clean"); run("opt_lut"); } - + if (check_label("iomap", "(for qlf_k6n10f, skip if -noioff)") && (family == "qlf_k6n10f" || help_mode)) { if (ioff || help_mode) { run("ql_ioff"); diff --git a/techlibs/sf2/NOTES.txt b/techlibs/sf2/NOTES.txt index 6204d8fee..0e4fdb16b 100644 --- a/techlibs/sf2/NOTES.txt +++ b/techlibs/sf2/NOTES.txt @@ -51,8 +51,8 @@ Then you can use the normal flow. This is done by the run_yosys.tcl: ----------- run_yosys.tcl -------------- open_project -file {./top.prjx} -run_tool -name {PLACEROUTE} -run_tool -name {PROGRAMDEVICE} +run_tool -name {PLACEROUTE} +run_tool -name {PROGRAMDEVICE} ----------------------------------------- diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index db012f169..0bf4ea18c 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -178,7 +178,7 @@ module testbench; {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; {ALUMODE, INMODE} = $urandom; CARRYINSEL = $urandom & $urandom & $urandom; - OPMODE = $urandom; + OPMODE = $urandom; if ($urandom & 1'b1) OPMODE[3:0] = 4'b0101; // test multiply more than other modes {CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom; diff --git a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v index 853ba6254..a584766b8 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v @@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, parameter WIDTHA = 4; parameter SIZEA = 1024; parameter ADDRWIDTHA = 10; - + parameter WIDTHB = 16; parameter SIZEB = 256; parameter ADDRWIDTHB = 8; diff --git a/tests/arch/analogdevices/attributes_test.ys b/tests/arch/analogdevices/attributes_test.ys index 03d6decff..a6b2242ff 100644 --- a/tests/arch/analogdevices/attributes_test.ys +++ b/tests/arch/analogdevices/attributes_test.ys @@ -4,7 +4,7 @@ hierarchy -top block_ram synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module # select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive. - + # Check that distributed memory without parameters is not modified design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -13,7 +13,7 @@ synth_analogdevices -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module select -assert-count 8 t:RAMS64X1 select -assert-count 8 t:FFRE - + # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -22,7 +22,7 @@ synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 64 t:RAMS64X1 select -assert-count 4 t:FFRE - + # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -30,7 +30,7 @@ setattr -set logic_block 1 block_ram/m:* synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 0 t:RBRAM2 - + # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v diff --git a/tests/arch/analogdevices/blockram.ys b/tests/arch/analogdevices/blockram.ys index f6efa5ba8..fb829abaa 100644 --- a/tests/arch/analogdevices/blockram.ys +++ b/tests/arch/analogdevices/blockram.ys @@ -54,7 +54,7 @@ select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp @@ -62,7 +62,7 @@ select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp diff --git a/tests/arch/analogdevices/bug1598.ys b/tests/arch/analogdevices/bug1598.ys index a4884510d..1397b7506 100644 --- a/tests/arch/analogdevices/bug1598.ys +++ b/tests/arch/analogdevices/bug1598.ys @@ -3,14 +3,14 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc -equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices diff --git a/tests/arch/analogdevices/dsp_abc9.ys b/tests/arch/analogdevices/dsp_abc9.ys index ad27a9d6e..99a057fe4 100644 --- a/tests/arch/analogdevices/dsp_abc9.ys +++ b/tests/arch/analogdevices/dsp_abc9.ys @@ -17,7 +17,7 @@ module top(input signed [24:0] A, input signed [17:0] B, output [47:0] P); assign P = A * B; endmodule EOT -synth_analogdevices +synth_analogdevices techmap -autoproc -wb -map +/analogdevices/cells_sim.v opt -full -fine select -assert-count 2 t:$mul @@ -34,7 +34,7 @@ EOT async2sync techmap -map +/analogdevices/dsp_map.v verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1 -synth_analogdevices +synth_analogdevices techmap -autoproc -wb -map +/analogdevices/cells_sim.v opt -full -fine select -assert-count 0 t:* t:$assert %d diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 2f37ff944..c00dc6d96 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -233,7 +233,7 @@ endmodule // double_sync_ram_sdp module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) - (input wire clk_a, clk_b, + (input wire clk_a, clk_b, input wire write_enable_a, write_enable_b, input wire read_enable_a, read_enable_b, input wire [DATA_WIDTH-1:0] write_data_a, write_data_b, diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v index cf1c21a58..3d96674c7 100644 --- a/tests/arch/common/fsm.v +++ b/tests/arch/common/fsm.v @@ -19,7 +19,7 @@ state <= #1 IDLE; gnt_0 <= 0; gnt_1 <= 0; - end + end else case(state) IDLE : if (req_0 == 1'b1) begin diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index 06e63c9af..589e2d29f 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -13,5 +13,5 @@ module top(out, clk, in); begin out <= out >> 1; out[7] <= in; - end + end endmodule diff --git a/tests/arch/ecp5/bug1598.ys b/tests/arch/ecp5/bug1598.ys index 1d1682fcd..d997bc7c9 100644 --- a/tests/arch/ecp5/bug1598.ys +++ b/tests/arch/ecp5/bug1598.ys @@ -3,13 +3,13 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys index f075182c8..cca5a7648 100644 --- a/tests/arch/ecp5/memories.ys +++ b/tests/arch/ecp5/memories.ys @@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp hierarchy -top sync_ram_tdp synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp -select -assert-count 1 t:DP16KD +select -assert-count 1 t:DP16KD select -assert-none t:LUT4 diff --git a/tests/arch/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys index 3f0079f4a..e39a4fcbc 100644 --- a/tests/arch/ecp5/shifter.ys +++ b/tests/arch/ecp5/shifter.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - + select -assert-count 8 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys index 8438cb979..6ea04b6fd 100644 --- a/tests/arch/ice40/bug1598.ys +++ b/tests/arch/ice40/bug1598.ys @@ -3,13 +3,13 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys index 16f8283a0..92ce8eec9 100644 --- a/tests/arch/ice40/bug1626.ys +++ b/tests/arch/ice40/bug1626.ys @@ -182,20 +182,20 @@ module \ahb_async_sram_halfwidth attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72" switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y case 1'1 - case + case attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78" switch \ahbls_hready case 1'1 attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79" switch \ahbls_htrans [1] case 1'1 - case + case end - case + case attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y case 1'1 - case + case end end end diff --git a/tests/arch/ice40/ice40_dsp_const.ys b/tests/arch/ice40/ice40_dsp_const.ys index 735f945a1..893f681ed 100644 --- a/tests/arch/ice40/ice40_dsp_const.ys +++ b/tests/arch/ice40/ice40_dsp_const.ys @@ -75,7 +75,7 @@ EOT techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v async2sync -equiv_make top ref equiv -select -assert-any -module equiv t:$equiv -equiv_induct +equiv_make top ref equiv +select -assert-any -module equiv t:$equiv +equiv_induct equiv_status -assert diff --git a/tests/arch/ice40/spram.v b/tests/arch/ice40/spram.v index 4e1aef2c6..fb55aa7d9 100644 --- a/tests/arch/ice40/spram.v +++ b/tests/arch/ice40/spram.v @@ -6,7 +6,7 @@ parameter SKIP_RDEN = 1; input clk; input write_enable, read_enable; input [DATA_WIDTH - 1 : 0] write_data; -input [ADDR_WIDTH - 1 : 0] addr; +input [ADDR_WIDTH - 1 : 0] addr; output [DATA_WIDTH - 1 : 0] read_data; (* ram_style = "huge" *) diff --git a/tests/arch/microchip/dff.ys b/tests/arch/microchip/dff.ys index 04fdcfc92..9b6e03f5a 100644 --- a/tests/arch/microchip/dff.ys +++ b/tests/arch/microchip/dff.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/dff_opt.ys b/tests/arch/microchip/dff_opt.ys index 52e96935d..d12bed1d4 100644 --- a/tests/arch/microchip/dff_opt.ys +++ b/tests/arch/microchip/dff_opt.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/dsp.ys b/tests/arch/microchip/dsp.ys index b02ad624a..a616851cd 100644 --- a/tests/arch/microchip/dsp.ys +++ b/tests/arch/microchip/dsp.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -120,7 +120,7 @@ output reg cout; input [n:0] a; input [n:0] b; input [n-1:0] c; - always @(*) + always @(*) begin {cout,out} = a * b + c; end diff --git a/tests/arch/microchip/mult.ys b/tests/arch/microchip/mult.ys index 7a82e52ec..36164fd58 100644 --- a/tests/arch/microchip/mult.ys +++ b/tests/arch/microchip/mult.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/ram_SDP.ys b/tests/arch/microchip/ram_SDP.ys index 1b8bffc36..3ba49f0dd 100644 --- a/tests/arch/microchip/ram_SDP.ys +++ b/tests/arch/microchip/ram_SDP.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -27,7 +27,7 @@ output reg [d_width-1:0] q; reg [d_width-1:0] mem [mem_depth-1:0]; always @(posedge clk) begin - if (we) begin + if (we) begin mem[waddr] <= data; end else begin q <= mem[waddr]; diff --git a/tests/arch/microchip/ram_TDP.ys b/tests/arch/microchip/ram_TDP.ys index 79db0456c..21e72ed9b 100644 --- a/tests/arch/microchip/ram_TDP.ys +++ b/tests/arch/microchip/ram_TDP.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -28,7 +28,7 @@ reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0]; always @ (posedge clka) begin addra_reg <= addra; - + if(wea) begin mem[addra] <= dataina; qa <= dataina; diff --git a/tests/arch/microchip/reduce.ys b/tests/arch/microchip/reduce.ys index 07f25a3d1..45ca72eaa 100644 --- a/tests/arch/microchip/reduce.ys +++ b/tests/arch/microchip/reduce.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/simple_ram.ys b/tests/arch/microchip/simple_ram.ys index 22e3b9317..7bb6318f0 100644 --- a/tests/arch/microchip/simple_ram.ys +++ b/tests/arch/microchip/simple_ram.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/uram_ar.ys b/tests/arch/microchip/uram_ar.ys index 95c3fbf41..208714824 100644 --- a/tests/arch/microchip/uram_ar.ys +++ b/tests/arch/microchip/uram_ar.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -28,7 +28,7 @@ reg [d_width-1:0] mem [mem_depth-1:0]; assign q = mem[waddr]; always @(posedge clk) begin - if (we) + if (we) mem[waddr] <= data; end diff --git a/tests/arch/microchip/uram_sr.ys b/tests/arch/microchip/uram_sr.ys index 338ce5ecc..a3ddb1835 100644 --- a/tests/arch/microchip/uram_sr.ys +++ b/tests/arch/microchip/uram_sr.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -32,7 +32,7 @@ module uram_sr(clk, wr, raddr, din, waddr, dout); end always@(posedge clk) begin - raddr_reg <= raddr; + raddr_reg <= raddr; if(wr) mem[waddr]<= din; end diff --git a/tests/arch/microchip/widemux.ys b/tests/arch/microchip/widemux.ys index b066dd540..78d6860d0 100644 --- a/tests/arch/microchip/widemux.ys +++ b/tests/arch/microchip/widemux.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/nanoxplore/meminit.v b/tests/arch/nanoxplore/meminit.v index 24d5a57f7..c0896523c 100644 --- a/tests/arch/nanoxplore/meminit.v +++ b/tests/arch/nanoxplore/meminit.v @@ -31,7 +31,7 @@ always @(posedge clk) begin read_addr <= counter; read_val <= mem[counter]; end else begin - did_read <= 1'b0; + did_read <= 1'b0; end if (!done) diff --git a/tests/arch/nanoxplore/meminit.ys b/tests/arch/nanoxplore/meminit.ys index ca93e6500..1209b0d6c 100644 --- a/tests/arch/nanoxplore/meminit.ys +++ b/tests/arch/nanoxplore/meminit.ys @@ -3,7 +3,7 @@ chparam -set DEPTH_LOG2 5 -set WIDTH 36 prep opt_dff prep -rdff -synth_nanoxplore +synth_nanoxplore clean_zerowidth select -assert-none t:$mem_v2 t:$mem read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v @@ -18,7 +18,7 @@ chparam -set DEPTH_LOG2 6 -set WIDTH 18 prep opt_dff prep -rdff -synth_nanoxplore +synth_nanoxplore clean_zerowidth select -assert-none t:$mem_v2 t:$mem read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v @@ -34,7 +34,7 @@ chparam -set DEPTH_LOG2 8 -set WIDTH 18 prep opt_dff prep -rdff -synth_nanoxplore +synth_nanoxplore clean_zerowidth select -assert-none t:$mem_v2 t:$mem read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v diff --git a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys index e12963ae6..78bd221cc 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys @@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dff # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre -select -assert-none t:sdffsre %% t:* %D +select -assert-none t:sdffsre %% t:* %D design -load read hierarchy -top my_dffe @@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dffe # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre -select -assert-none t:sdffsre %% t:* %D +select -assert-none t:sdffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index a0d15bd62..988aceaca 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -46,7 +46,7 @@ initial begin end `MEM_TEST_VECTOR - + end @@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i]; always @(posedge clk) begin if (i < VECTORLEN-1) begin if (i > 0) begin - if($past(rce_a)) + if($past(rce_a)) assert(rq_a == rq_a_e); if($past(rce_b)) assert(rq_b == rq_b_e); diff --git a/tests/arch/quicklogic/qlf_k6n10f/meminit.v b/tests/arch/quicklogic/qlf_k6n10f/meminit.v index 46a7dcac7..afc525656 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/meminit.v +++ b/tests/arch/quicklogic/qlf_k6n10f/meminit.v @@ -31,7 +31,7 @@ always @(posedge clk) begin read_addr <= counter; read_val <= mem[counter]; end else begin - did_read <= 1'b0; + did_read <= 1'b0; end if (!done) diff --git a/tests/arch/xilinx/asym_ram_sdp_read_wider.v b/tests/arch/xilinx/asym_ram_sdp_read_wider.v index 49080c836..fec464e48 100644 --- a/tests/arch/xilinx/asym_ram_sdp_read_wider.v +++ b/tests/arch/xilinx/asym_ram_sdp_read_wider.v @@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, parameter WIDTHA = 4; parameter SIZEA = 1024; parameter ADDRWIDTHA = 10; - + parameter WIDTHB = 16; parameter SIZEB = 256; parameter ADDRWIDTHB = 8; diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys index 74861850f..16dad6dbf 100644 --- a/tests/arch/xilinx/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -4,7 +4,7 @@ hierarchy -top block_ram synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 - + # Check that distributed memory without parameters is not modified design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -12,7 +12,7 @@ hierarchy -top distributed_ram synth_xilinx -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module select -assert-count 1 t:RAM32M - + # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -20,7 +20,7 @@ setattr -set ram_style "distributed" block_ram/m:* synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 16 t:RAM256X1S - + # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -28,7 +28,7 @@ setattr -set logic_block 1 block_ram/m:* synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 0 t:RAMB18E1 - + # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index c2b7aede7..96da72eaa 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp @@ -58,7 +58,7 @@ select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp diff --git a/tests/arch/xilinx/bug1598.ys b/tests/arch/xilinx/bug1598.ys index 1175380b1..f495b9b78 100644 --- a/tests/arch/xilinx/bug1598.ys +++ b/tests/arch/xilinx/bug1598.ys @@ -3,13 +3,13 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v index 29920da41..059109275 100644 --- a/tests/arch/xilinx/xilinx_srl.v +++ b/tests/arch/xilinx/xilinx_srl.v @@ -34,7 +34,7 @@ parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; reg [DEPTH-1:0] r = INIT; wire clk = C ^ CLKPOL; always @(posedge C) - if (E) + if (E) r <= { r[DEPTH-2:0], D }; assign Q = r[L]; endmodule diff --git a/tests/asicworld/code_hdl_models_GrayCounter.v b/tests/asicworld/code_hdl_models_GrayCounter.v index 23f0da04b..88e2972a4 100644 --- a/tests/asicworld/code_hdl_models_GrayCounter.v +++ b/tests/asicworld/code_hdl_models_GrayCounter.v @@ -6,19 +6,19 @@ module GrayCounter #(parameter COUNTER_WIDTH = 4) - + (output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output. - + input wire Enable_in, //Count enable. input wire Clear_in, //Count reset. - + input wire Clk); /////////Internal connections & variables/////// reg [COUNTER_WIDTH-1:0] BinaryCount; /////////Code/////////////////////// - + always @ (posedge Clk) if (Clear_in) begin BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with @@ -29,5 +29,5 @@ module GrayCounter GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1], BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]}; end - + endmodule diff --git a/tests/asicworld/code_hdl_models_arbiter.v b/tests/asicworld/code_hdl_models_arbiter.v index d3e3a66f1..3119f0580 100644 --- a/tests/asicworld/code_hdl_models_arbiter.v +++ b/tests/asicworld/code_hdl_models_arbiter.v @@ -3,32 +3,32 @@ // orginally coded by WD Peterson in VHDL. //---------------------------------------------------- module arbiter ( - clk, - rst, - req3, - req2, - req1, - req0, - gnt3, - gnt2, - gnt1, - gnt0 + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 ); -// --------------Port Declaration----------------------- -input clk; -input rst; -input req3; -input req2; -input req1; -input req0; -output gnt3; -output gnt2; -output gnt1; -output gnt0; +// --------------Port Declaration----------------------- +input clk; +input rst; +input req3; +input req2; +input req1; +input req0; +output gnt3; +output gnt2; +output gnt1; +output gnt0; //--------------Internal Registers---------------------- -wire [1:0] gnt ; -wire comreq ; +wire [1:0] gnt ; +wire comreq ; wire beg ; wire [1:0] lgnt ; wire lcomreq ; @@ -41,14 +41,14 @@ reg lmask0 ; reg lmask1 ; reg ledge ; -//--------------Code Starts Here----------------------- +//--------------Code Starts Here----------------------- always @ (posedge clk) if (rst) begin lgnt0 <= 0; lgnt1 <= 0; lgnt2 <= 0; lgnt3 <= 0; -end else begin +end else begin lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0) | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0) | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0) @@ -69,18 +69,18 @@ end else begin | (~lcomreq & lmask1 & ~lmask0 & req3) | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0) | ( lcomreq & lgnt3); -end +end //---------------------------------------------------- // lasmask state machine. //---------------------------------------------------- assign beg = (req3 | req2 | req1 | req0) & ~lcomreq; always @ (posedge clk) -begin +begin lasmask <= (beg & ~ledge & ~lasmask); - ledge <= (beg & ~ledge & lasmask) + ledge <= (beg & ~ledge & lasmask) | (beg & ledge & ~lasmask); -end +end //---------------------------------------------------- // comreq logic. @@ -108,7 +108,7 @@ end else if(lasmask) begin end else begin lmask1 <= lmask1; lmask0 <= lmask0; -end +end assign comreq = lcomreq; assign gnt = lgnt; diff --git a/tests/asicworld/code_hdl_models_arbiter_tb.v b/tests/asicworld/code_hdl_models_arbiter_tb.v index 78d1168e6..6d28ea23b 100644 --- a/tests/asicworld/code_hdl_models_arbiter_tb.v +++ b/tests/asicworld/code_hdl_models_arbiter_tb.v @@ -6,10 +6,10 @@ reg req3 = 0; reg req2 = 0; reg req1 = 0; reg req0 = 0; -wire gnt3; -wire gnt2; -wire gnt1; -wire gnt0; +wire gnt3; +wire gnt2; +wire gnt1; +wire gnt0; // Clock generator always #1 clk = ~clk; @@ -41,20 +41,20 @@ initial begin req0 <= 0; repeat (1) @ (posedge clk); #10 $finish; -end +end // Connect the DUT arbiter U ( - clk, - rst, - req3, - req2, - req1, - req0, - gnt3, - gnt2, - gnt1, - gnt0 + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 ); endmodule diff --git a/tests/asicworld/code_hdl_models_cam.v b/tests/asicworld/code_hdl_models_cam.v index 0cebc07cc..781ccdf98 100644 --- a/tests/asicworld/code_hdl_models_cam.v +++ b/tests/asicworld/code_hdl_models_cam.v @@ -9,18 +9,18 @@ clk , // Cam clock cam_enable , // Cam enable cam_data_in , // Cam data to match cam_hit_out , // Cam match has happened -cam_addr_out // Cam output address +cam_addr_out // Cam output address ); parameter ADDR_WIDTH = 8; parameter DEPTH = 1 << ADDR_WIDTH; //------------Input Ports-------------- -input clk; -input cam_enable; -input [DEPTH-1:0] cam_data_in; +input clk; +input cam_enable; +input [DEPTH-1:0] cam_data_in; //----------Output Ports-------------- -output cam_hit_out; -output [ADDR_WIDTH-1:0] cam_addr_out; +output cam_hit_out; +output [ADDR_WIDTH-1:0] cam_addr_out; //------------Internal Variables-------- reg [ADDR_WIDTH-1:0] cam_addr_out; reg cam_hit_out; @@ -46,7 +46,7 @@ always @(cam_data_in) begin end end -// Register the outputs +// Register the outputs always @(posedge clk) begin if (cam_enable) begin cam_hit_out <= cam_hit_combo; @@ -57,4 +57,4 @@ always @(posedge clk) begin end end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_clk_div.v b/tests/asicworld/code_hdl_models_clk_div.v index c48ab0dd0..ae4e7edfb 100644 --- a/tests/asicworld/code_hdl_models_clk_div.v +++ b/tests/asicworld/code_hdl_models_clk_div.v @@ -6,7 +6,7 @@ //----------------------------------------------------- module clk_div (clk_in, enable,reset, clk_out); - // --------------Port Declaration----------------------- + // --------------Port Declaration----------------------- input clk_in ; input reset ; input enable ; @@ -16,12 +16,12 @@ module clk_div (clk_in, enable,reset, clk_out); wire enable ; //--------------Internal Registers---------------------- reg clk_out ; -//--------------Code Starts Here----------------------- -always @ (posedge clk_in) -if (reset) begin +//--------------Code Starts Here----------------------- +always @ (posedge clk_in) +if (reset) begin clk_out <= 1'b0; end else if (enable) begin - clk_out <= !clk_out ; + clk_out <= !clk_out ; end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_clk_div_45.v b/tests/asicworld/code_hdl_models_clk_div_45.v index d9d289673..e40820c52 100644 --- a/tests/asicworld/code_hdl_models_clk_div_45.v +++ b/tests/asicworld/code_hdl_models_clk_div_45.v @@ -28,7 +28,7 @@ reg toggle2 ; //--------------Code Starts Here----------------------- always @ (posedge clk_in) -if (enable == 1'b0) begin +if (enable == 1'b0) begin counter1 <= 4'b0; toggle1 <= 0; end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin @@ -37,7 +37,7 @@ end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin end else begin counter1 <= counter1 + 1; end - + always @ (negedge clk_in) if (enable == 1'b0) begin counter2 <= 4'b0; diff --git a/tests/asicworld/code_hdl_models_decoder_using_assign.v b/tests/asicworld/code_hdl_models_decoder_using_assign.v index ec0dc95b2..69a8e1aec 100644 --- a/tests/asicworld/code_hdl_models_decoder_using_assign.v +++ b/tests/asicworld/code_hdl_models_decoder_using_assign.v @@ -6,14 +6,14 @@ //----------------------------------------------------- module decoder_using_assign ( binary_in , // 4 bit binary input -decoder_out , // 16-bit out +decoder_out , // 16-bit out enable // Enable for the decoder ); input [3:0] binary_in ; -input enable ; -output [15:0] decoder_out ; - -wire [15:0] decoder_out ; +input enable ; +output [15:0] decoder_out ; + +wire [15:0] decoder_out ; assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ; diff --git a/tests/asicworld/code_hdl_models_dff_async_reset.v b/tests/asicworld/code_hdl_models_dff_async_reset.v index a156082f4..cfda75a8a 100644 --- a/tests/asicworld/code_hdl_models_dff_async_reset.v +++ b/tests/asicworld/code_hdl_models_dff_async_reset.v @@ -7,11 +7,11 @@ module dff_async_reset ( data , // Data Input clk , // Clock Input -reset , // Reset input +reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; diff --git a/tests/asicworld/code_hdl_models_dff_sync_reset.v b/tests/asicworld/code_hdl_models_dff_sync_reset.v index 7ef404548..0efb4c840 100644 --- a/tests/asicworld/code_hdl_models_dff_sync_reset.v +++ b/tests/asicworld/code_hdl_models_dff_sync_reset.v @@ -11,7 +11,7 @@ reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; diff --git a/tests/asicworld/code_hdl_models_encoder_using_case.v b/tests/asicworld/code_hdl_models_encoder_using_case.v index 32e1b720f..91bafb99c 100644 --- a/tests/asicworld/code_hdl_models_encoder_using_case.v +++ b/tests/asicworld/code_hdl_models_encoder_using_case.v @@ -10,31 +10,31 @@ encoder_in , // 16-bit Input enable // Enable for the encoder ); output [3:0] binary_out ; -input enable ; -input [15:0] encoder_in ; - +input enable ; +input [15:0] encoder_in ; + reg [3:0] binary_out ; - + always @ (enable or encoder_in) begin binary_out = 0; if (enable) begin - case (encoder_in) - 16'h0002 : binary_out = 1; - 16'h0004 : binary_out = 2; - 16'h0008 : binary_out = 3; + case (encoder_in) + 16'h0002 : binary_out = 1; + 16'h0004 : binary_out = 2; + 16'h0008 : binary_out = 3; 16'h0010 : binary_out = 4; - 16'h0020 : binary_out = 5; - 16'h0040 : binary_out = 6; - 16'h0080 : binary_out = 7; + 16'h0020 : binary_out = 5; + 16'h0040 : binary_out = 6; + 16'h0080 : binary_out = 7; 16'h0100 : binary_out = 8; 16'h0200 : binary_out = 9; - 16'h0400 : binary_out = 10; - 16'h0800 : binary_out = 11; - 16'h1000 : binary_out = 12; - 16'h2000 : binary_out = 13; - 16'h4000 : binary_out = 14; - 16'h8000 : binary_out = 15; + 16'h0400 : binary_out = 10; + 16'h0800 : binary_out = 11; + 16'h1000 : binary_out = 12; + 16'h2000 : binary_out = 13; + 16'h4000 : binary_out = 14; + 16'h8000 : binary_out = 15; endcase end end diff --git a/tests/asicworld/code_hdl_models_encoder_using_if.v b/tests/asicworld/code_hdl_models_encoder_using_if.v index 2c97ddba6..3f559b60e 100644 --- a/tests/asicworld/code_hdl_models_encoder_using_if.v +++ b/tests/asicworld/code_hdl_models_encoder_using_if.v @@ -8,51 +8,51 @@ module encoder_using_if( binary_out , // 4 bit binary output encoder_in , // 16-bit input enable // Enable for the encoder -); +); //-----------Output Ports--------------- output [3:0] binary_out ; //-----------Input Ports--------------- -input enable ; -input [15:0] encoder_in ; +input enable ; +input [15:0] encoder_in ; //------------Internal Variables-------- -reg [3:0] binary_out ; +reg [3:0] binary_out ; //-------------Code Start----------------- always @ (enable or encoder_in) - begin - binary_out = 0; + begin + binary_out = 0; if (enable) begin if (encoder_in == 16'h0002) begin binary_out = 1; - end if (encoder_in == 16'h0004) begin - binary_out = 2; - end if (encoder_in == 16'h0008) begin - binary_out = 3; - end if (encoder_in == 16'h0010) begin - binary_out = 4; - end if (encoder_in == 16'h0020) begin - binary_out = 5; - end if (encoder_in == 16'h0040) begin - binary_out = 6; - end if (encoder_in == 16'h0080) begin - binary_out = 7; - end if (encoder_in == 16'h0100) begin - binary_out = 8; - end if (encoder_in == 16'h0200) begin - binary_out = 9; - end if (encoder_in == 16'h0400) begin - binary_out = 10; - end if (encoder_in == 16'h0800) begin - binary_out = 11; + end if (encoder_in == 16'h0004) begin + binary_out = 2; + end if (encoder_in == 16'h0008) begin + binary_out = 3; + end if (encoder_in == 16'h0010) begin + binary_out = 4; + end if (encoder_in == 16'h0020) begin + binary_out = 5; + end if (encoder_in == 16'h0040) begin + binary_out = 6; + end if (encoder_in == 16'h0080) begin + binary_out = 7; + end if (encoder_in == 16'h0100) begin + binary_out = 8; + end if (encoder_in == 16'h0200) begin + binary_out = 9; + end if (encoder_in == 16'h0400) begin + binary_out = 10; + end if (encoder_in == 16'h0800) begin + binary_out = 11; end if (encoder_in == 16'h1000) begin - binary_out = 12; - end if (encoder_in == 16'h2000) begin + binary_out = 12; + end if (encoder_in == 16'h2000) begin binary_out = 13; - end if (encoder_in == 16'h4000) begin - binary_out = 14; - end if (encoder_in == 16'h8000) begin - binary_out = 15; + end if (encoder_in == 16'h4000) begin + binary_out = 14; + end if (encoder_in == 16'h8000) begin + binary_out = 15; end end end - + endmodule diff --git a/tests/asicworld/code_hdl_models_gray_counter.v b/tests/asicworld/code_hdl_models_gray_counter.v index bc1e740ab..2b9bdb65f 100644 --- a/tests/asicworld/code_hdl_models_gray_counter.v +++ b/tests/asicworld/code_hdl_models_gray_counter.v @@ -10,24 +10,24 @@ module gray_counter ( clk , // clock rst // active hight reset ); - + //------------Input Ports-------------- - input clk, rst, enable; + input clk, rst, enable; //----------Output Ports---------------- output [ 7:0] out; //------------Internal Variables-------- wire [7:0] out; reg [7:0] count; //-------------Code Starts Here--------- - always @ (posedge clk) - if (rst) - count <= 0; - else if (enable) - count <= count + 1; - - assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ - count[5]),(count[5] ^ count[4]), (count[4] ^ - count[3]),(count[3] ^ count[2]), (count[2] ^ + always @ (posedge clk) + if (rst) + count <= 0; + else if (enable) + count <= count + 1; + + assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ + count[5]),(count[5] ^ count[4]), (count[4] ^ + count[3]),(count[3] ^ count[2]), (count[2] ^ count[1]),(count[1] ^ count[0]) }; - -endmodule + +endmodule diff --git a/tests/asicworld/code_hdl_models_lfsr.v b/tests/asicworld/code_hdl_models_lfsr.v index 639780832..b0902e630 100644 --- a/tests/asicworld/code_hdl_models_lfsr.v +++ b/tests/asicworld/code_hdl_models_lfsr.v @@ -30,6 +30,6 @@ end else if (enable) begin out[4],out[3], out[2],out[1], out[0], linear_feedback}; -end +end endmodule // End Of Module counter diff --git a/tests/asicworld/code_hdl_models_lfsr_updown.v b/tests/asicworld/code_hdl_models_lfsr_updown.v index 0bd29b835..d40a586ef 100644 --- a/tests/asicworld/code_hdl_models_lfsr_updown.v +++ b/tests/asicworld/code_hdl_models_lfsr_updown.v @@ -1,4 +1,4 @@ -`define WIDTH 8 +`define WIDTH 8 module lfsr_updown ( clk , // Clock input reset , // Reset input @@ -10,7 +10,7 @@ overflow // Overflow output input clk; input reset; - input enable; + input enable; input up_down; output [`WIDTH-1 : 0] count; @@ -18,11 +18,11 @@ overflow // Overflow output reg [`WIDTH-1 : 0] count; - assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) : + assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) : (count == {1'b1, {`WIDTH-1{1'b0}}}) ; always @(posedge clk) - if (reset) + if (reset) count <= {`WIDTH{1'b0}}; else if (enable) begin if (up_down) begin diff --git a/tests/asicworld/code_hdl_models_mux_using_case.v b/tests/asicworld/code_hdl_models_mux_using_case.v index 123da4483..8d60c6662 100644 --- a/tests/asicworld/code_hdl_models_mux_using_case.v +++ b/tests/asicworld/code_hdl_models_mux_using_case.v @@ -19,10 +19,10 @@ reg mux_out; //-------------Code Starts Here--------- always @ (sel or din_0 or din_1) begin : MUX - case(sel ) + case(sel ) 1'b0 : mux_out = din_0; 1'b1 : mux_out = din_1; - endcase + endcase end endmodule //End Of Module mux diff --git a/tests/asicworld/code_hdl_models_one_hot_cnt.v b/tests/asicworld/code_hdl_models_one_hot_cnt.v index f6b84c6e5..e4d50b585 100644 --- a/tests/asicworld/code_hdl_models_one_hot_cnt.v +++ b/tests/asicworld/code_hdl_models_one_hot_cnt.v @@ -17,7 +17,7 @@ output [7:0] out; input enable, clk, reset; //------------Internal Variables-------- -reg [7:0] out; +reg [7:0] out; //-------------Code Starts Here------- always @ (posedge clk) @@ -28,4 +28,4 @@ end else if (enable) begin out[2],out[1],out[0],out[7]}; end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_parallel_crc.v b/tests/asicworld/code_hdl_models_parallel_crc.v index d8d0bf1c6..8e9aad27f 100644 --- a/tests/asicworld/code_hdl_models_parallel_crc.v +++ b/tests/asicworld/code_hdl_models_parallel_crc.v @@ -8,8 +8,8 @@ module parallel_crc_ccitt ( clk , reset , enable , -init , -data_in , +init , +data_in , crc_out ); //-----------Input Ports--------------- diff --git a/tests/asicworld/code_hdl_models_parity_using_assign.v b/tests/asicworld/code_hdl_models_parity_using_assign.v index b0282e8d7..e676a8f49 100644 --- a/tests/asicworld/code_hdl_models_parity_using_assign.v +++ b/tests/asicworld/code_hdl_models_parity_using_assign.v @@ -9,13 +9,13 @@ data_in , // 8 bit data in parity_out // 1 bit parity out ); output parity_out ; -input [7:0] data_in ; - +input [7:0] data_in ; + wire parity_out ; - -assign parity_out = (data_in[0] ^ data_in[1]) ^ - (data_in[2] ^ data_in[3]) ^ - (data_in[4] ^ data_in[5]) ^ + +assign parity_out = (data_in[0] ^ data_in[1]) ^ + (data_in[2] ^ data_in[3]) ^ + (data_in[4] ^ data_in[5]) ^ (data_in[6] ^ data_in[7]); -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_parity_using_bitwise.v b/tests/asicworld/code_hdl_models_parity_using_bitwise.v index 0046fb143..36e8931b8 100644 --- a/tests/asicworld/code_hdl_models_parity_using_bitwise.v +++ b/tests/asicworld/code_hdl_models_parity_using_bitwise.v @@ -9,8 +9,8 @@ data_in , // 8 bit data in parity_out // 1 bit parity out ); output parity_out ; -input [7:0] data_in ; - -assign parity_out = ^data_in; +input [7:0] data_in ; + +assign parity_out = ^data_in; endmodule diff --git a/tests/asicworld/code_hdl_models_parity_using_function.v b/tests/asicworld/code_hdl_models_parity_using_function.v index 0d07aaebe..531c973e8 100644 --- a/tests/asicworld/code_hdl_models_parity_using_function.v +++ b/tests/asicworld/code_hdl_models_parity_using_function.v @@ -9,21 +9,21 @@ data_in , // 8 bit data in parity_out // 1 bit parity out ); output parity_out ; -input [7:0] data_in ; - -wire parity_out ; +input [7:0] data_in ; + +wire parity_out ; function parity; - input [31:0] data; + input [31:0] data; begin - parity = (data_in[0] ^ data_in[1]) ^ - (data_in[2] ^ data_in[3]) ^ - (data_in[4] ^ data_in[5]) ^ + parity = (data_in[0] ^ data_in[1]) ^ + (data_in[2] ^ data_in[3]) ^ + (data_in[4] ^ data_in[5]) ^ (data_in[6] ^ data_in[7]); - end -endfunction - - + end +endfunction + + assign parity_out = parity(data_in); endmodule diff --git a/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v b/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v index c1ce960c4..5c3784e9b 100644 --- a/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v +++ b/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v @@ -6,31 +6,31 @@ //----------------------------------------------------- module pri_encoder_using_assign ( binary_out , // 4 bit binary output -encoder_in , // 16-bit input +encoder_in , // 16-bit input enable // Enable for the encoder ); output [3:0] binary_out ; -input enable ; -input [15:0] encoder_in ; +input enable ; +input [15:0] encoder_in ; wire [3:0] binary_out ; - -assign binary_out = (!enable) ? 0 : ( - (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 : - (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 : - (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 : - (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 : - (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 : - (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 : - (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 : - (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 : - (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 : - (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 : - (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 : - (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 : - (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 : - (encoder_in == 16'bxx10_0000_0000_0000) ? 13 : - (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15); -endmodule +assign binary_out = (!enable) ? 0 : ( + (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 : + (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 : + (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 : + (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 : + (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 : + (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 : + (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 : + (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 : + (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 : + (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 : + (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 : + (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 : + (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 : + (encoder_in == 16'bxx10_0000_0000_0000) ? 13 : + (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15); + +endmodule diff --git a/tests/asicworld/code_hdl_models_rom_using_case.v b/tests/asicworld/code_hdl_models_rom_using_case.v index 6b700993b..1a0ee7949 100644 --- a/tests/asicworld/code_hdl_models_rom_using_case.v +++ b/tests/asicworld/code_hdl_models_rom_using_case.v @@ -7,7 +7,7 @@ module rom_using_case ( address , // Address input data , // Data output -read_en , // Read Enable +read_en , // Read Enable ce // Chip Enable ); input [3:0] address; @@ -16,7 +16,7 @@ input read_en; input ce; reg [7:0] data ; - + always @ (ce or read_en or address) begin case (address) diff --git a/tests/asicworld/code_hdl_models_serial_crc.v b/tests/asicworld/code_hdl_models_serial_crc.v index a4a63a26f..de4424e8c 100644 --- a/tests/asicworld/code_hdl_models_serial_crc.v +++ b/tests/asicworld/code_hdl_models_serial_crc.v @@ -8,8 +8,8 @@ module serial_crc_ccitt ( clk , reset , enable , -init , -data_in , +init , +data_in , crc_out ); //-----------Input Ports--------------- @@ -49,6 +49,6 @@ end else if (enable) begin lfsr[14] <= lfsr[13]; lfsr[15] <= lfsr[14]; end -end +end endmodule diff --git a/tests/asicworld/code_hdl_models_tff_async_reset.v b/tests/asicworld/code_hdl_models_tff_async_reset.v index 4c5a1fa9c..d45fcc330 100644 --- a/tests/asicworld/code_hdl_models_tff_async_reset.v +++ b/tests/asicworld/code_hdl_models_tff_async_reset.v @@ -11,7 +11,7 @@ reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- diff --git a/tests/asicworld/code_hdl_models_tff_sync_reset.v b/tests/asicworld/code_hdl_models_tff_sync_reset.v index a962d53d8..f9ecd3ae8 100644 --- a/tests/asicworld/code_hdl_models_tff_sync_reset.v +++ b/tests/asicworld/code_hdl_models_tff_sync_reset.v @@ -11,7 +11,7 @@ reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- diff --git a/tests/asicworld/code_hdl_models_uart.v b/tests/asicworld/code_hdl_models_uart.v index 40205250a..f8a5afaed 100644 --- a/tests/asicworld/code_hdl_models_uart.v +++ b/tests/asicworld/code_hdl_models_uart.v @@ -1,5 +1,5 @@ //----------------------------------------------------- -// Design Name : uart +// Design Name : uart // File Name : uart.v // Function : Simple UART // Coder : Deepak Kumar Tala @@ -34,7 +34,7 @@ input rx_enable ; input rx_in ; output rx_empty ; -// Internal Variables +// Internal Variables reg [7:0] tx_reg ; reg tx_empty ; reg tx_over_run ; @@ -43,7 +43,7 @@ reg tx_out ; reg [7:0] rx_reg ; reg [7:0] rx_data ; reg [3:0] rx_sample_cnt ; -reg [3:0] rx_cnt ; +reg [3:0] rx_cnt ; reg rx_frame_err ; reg rx_over_run ; reg rx_empty ; @@ -54,7 +54,7 @@ reg rx_busy ; // UART RX Logic always @ (posedge rxclk or posedge reset) if (reset) begin - rx_reg <= 0; + rx_reg <= 0; rx_data <= 0; rx_sample_cnt <= 0; rx_cnt <= 0; @@ -89,7 +89,7 @@ end else begin if ((rx_d2 == 1) && (rx_cnt == 0)) begin rx_busy <= 0; end else begin - rx_cnt <= rx_cnt + 1; + rx_cnt <= rx_cnt + 1; // Start storing the rx data if (rx_cnt > 0 && rx_cnt < 9) begin rx_reg[rx_cnt - 1] <= rx_d2; @@ -107,8 +107,8 @@ end else begin end end end - end - end + end + end end if (!rx_enable) begin rx_busy <= 0; diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v index 45dd08f16..4ebd58b21 100644 --- a/tests/asicworld/code_hdl_models_up_counter.v +++ b/tests/asicworld/code_hdl_models_up_counter.v @@ -25,4 +25,4 @@ end else if (enable) begin end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_up_counter_load.v b/tests/asicworld/code_hdl_models_up_counter_load.v index 92ad895aa..89645db58 100644 --- a/tests/asicworld/code_hdl_models_up_counter_load.v +++ b/tests/asicworld/code_hdl_models_up_counter_load.v @@ -14,7 +14,7 @@ reset // reset input ); //----------Output Ports-------------- output [7:0] out; -//------------Input Ports-------------- +//------------Input Ports-------------- input [7:0] data; input load, enable, clk, reset; //------------Internal Variables-------- @@ -28,5 +28,5 @@ end else if (load) begin end else if (enable) begin out <= out + 1; end - -endmodule + +endmodule diff --git a/tests/asicworld/code_hdl_models_up_down_counter.v b/tests/asicworld/code_hdl_models_up_down_counter.v index fff2982af..9a634edeb 100644 --- a/tests/asicworld/code_hdl_models_up_down_counter.v +++ b/tests/asicworld/code_hdl_models_up_down_counter.v @@ -12,7 +12,7 @@ reset // reset input ); //----------Output Ports-------------- output [7:0] out; -//------------Input Ports-------------- +//------------Input Ports-------------- input up_down, clk, reset; //------------Internal Variables-------- reg [7:0] out; @@ -26,4 +26,4 @@ end else begin out <= out - 1; end -endmodule +endmodule diff --git a/tests/asicworld/code_specman_switch_fabric.v b/tests/asicworld/code_specman_switch_fabric.v index 1ac7ee701..adf973798 100644 --- a/tests/asicworld/code_specman_switch_fabric.v +++ b/tests/asicworld/code_specman_switch_fabric.v @@ -22,28 +22,28 @@ output [7:0] data_out_ack3, data_out_ack4, data_out_ack5; (* gentb_clock *) wire clk; -switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0), - .data_in_valid(data_in_valid0), .data_out(data_out0), +switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0), + .data_in_valid(data_in_valid0), .data_out(data_out0), .data_out_ack(data_out_ack0)); -switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1), - .data_in_valid(data_in_valid1), .data_out(data_out1), +switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1), + .data_in_valid(data_in_valid1), .data_out(data_out1), .data_out_ack(data_out_ack1)); -switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2), +switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2), .data_in_valid(data_in_valid2), .data_out(data_out2), . data_out_ack(data_out_ack2)); -switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3), - .data_in_valid(data_in_valid3), .data_out(data_out3), +switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3), + .data_in_valid(data_in_valid3), .data_out(data_out3), .data_out_ack(data_out_ack3)); -switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4), - .data_in_valid(data_in_valid4), .data_out(data_out4), +switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4), + .data_in_valid(data_in_valid4), .data_out(data_out4), .data_out_ack(data_out_ack4)); -switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5), - .data_in_valid(data_in_valid5), .data_out(data_out5), +switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5), + .data_in_valid(data_in_valid5), .data_out(data_out5), .data_out_ack(data_out_ack5)); endmodule diff --git a/tests/asicworld/code_tidbits_asyn_reset.v b/tests/asicworld/code_tidbits_asyn_reset.v index 58e47c567..85bd71004 100644 --- a/tests/asicworld/code_tidbits_asyn_reset.v +++ b/tests/asicworld/code_tidbits_asyn_reset.v @@ -2,13 +2,13 @@ module asyn_reset(clk,reset,a,c); input clk; input reset; input a; - output c; + output c; wire clk; - wire reset; - wire a; + wire reset; + wire a; reg c; - + always @ (posedge clk or posedge reset) if ( reset == 1'b1) begin c <= 0; diff --git a/tests/asicworld/code_tidbits_blocking.v b/tests/asicworld/code_tidbits_blocking.v index e13b72cc7..79d67d937 100644 --- a/tests/asicworld/code_tidbits_blocking.v +++ b/tests/asicworld/code_tidbits_blocking.v @@ -2,16 +2,16 @@ module blocking (clk,a,c); input clk; input a; output c; - + wire clk; wire a; reg c; reg b; - + always @ (posedge clk ) begin b = a; c = b; end - + endmodule diff --git a/tests/asicworld/code_tidbits_fsm_using_always.v b/tests/asicworld/code_tidbits_fsm_using_always.v index 8a8775b95..7162bfa61 100644 --- a/tests/asicworld/code_tidbits_fsm_using_always.v +++ b/tests/asicworld/code_tidbits_fsm_using_always.v @@ -9,7 +9,7 @@ reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 -gnt_1 +gnt_1 ); //-------------Input Ports----------------------------- input clock,reset,req_0,req_1; diff --git a/tests/asicworld/code_tidbits_fsm_using_function.v b/tests/asicworld/code_tidbits_fsm_using_function.v index 404498a01..f97cd8521 100644 --- a/tests/asicworld/code_tidbits_fsm_using_function.v +++ b/tests/asicworld/code_tidbits_fsm_using_function.v @@ -9,7 +9,7 @@ reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 -gnt_1 +gnt_1 ); //-------------Input Ports----------------------------- input clock,reset,req_0,req_1; @@ -29,7 +29,7 @@ wire [SIZE-1:0] next_state ;// combo part of FSM assign next_state = fsm_function(state, req_0, req_1); //----------Function for Combo Logic----------------- function [SIZE-1:0] fsm_function; - input [SIZE-1:0] state ; + input [SIZE-1:0] state ; input req_0 ; input req_1 ; case(state) diff --git a/tests/asicworld/code_tidbits_fsm_using_single_always.v b/tests/asicworld/code_tidbits_fsm_using_single_always.v index 67cc08841..dc06154d3 100644 --- a/tests/asicworld/code_tidbits_fsm_using_single_always.v +++ b/tests/asicworld/code_tidbits_fsm_using_single_always.v @@ -10,7 +10,7 @@ reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 -gnt_1 +gnt_1 ); //=============Input Ports============================= input clock,reset,req_0,req_1; diff --git a/tests/asicworld/code_tidbits_nonblocking.v b/tests/asicworld/code_tidbits_nonblocking.v index 4a0d365e0..fd0e4ca74 100644 --- a/tests/asicworld/code_tidbits_nonblocking.v +++ b/tests/asicworld/code_tidbits_nonblocking.v @@ -2,16 +2,16 @@ module nonblocking (clk,a,c); input clk; input a; output c; - + wire clk; wire a; reg c; reg b; - + always @ (posedge clk ) begin b <= a; c <= b; end - + endmodule diff --git a/tests/asicworld/code_tidbits_reg_combo_example.v b/tests/asicworld/code_tidbits_reg_combo_example.v index 9689788c4..17765025a 100644 --- a/tests/asicworld/code_tidbits_reg_combo_example.v +++ b/tests/asicworld/code_tidbits_reg_combo_example.v @@ -6,7 +6,7 @@ reg y; wire a, b; always @ ( a or b) -begin +begin y = a & b; end diff --git a/tests/asicworld/code_tidbits_reg_seq_example.v b/tests/asicworld/code_tidbits_reg_seq_example.v index 458c87927..9627b9e04 100644 --- a/tests/asicworld/code_tidbits_reg_seq_example.v +++ b/tests/asicworld/code_tidbits_reg_seq_example.v @@ -1,7 +1,7 @@ module reg_seq_example( clk, reset, d, q); input clk, reset, d; output q; - + reg q; wire clk, reset, d; diff --git a/tests/asicworld/code_tidbits_syn_reset.v b/tests/asicworld/code_tidbits_syn_reset.v index 994771b16..37120eeee 100644 --- a/tests/asicworld/code_tidbits_syn_reset.v +++ b/tests/asicworld/code_tidbits_syn_reset.v @@ -1,19 +1,19 @@ module syn_reset (clk,reset,a,c); input clk; input reset; - input a; - output c; + input a; + output c; wire clk; - wire reset; - wire a; + wire reset; + wire a; reg c; - + always @ (posedge clk ) if ( reset == 1'b1) begin c <= 0; end else begin c <= a; end - -endmodule + +endmodule diff --git a/tests/asicworld/code_verilog_tutorial_always_example.v b/tests/asicworld/code_verilog_tutorial_always_example.v index 8b0fc2067..16174a17f 100644 --- a/tests/asicworld/code_verilog_tutorial_always_example.v +++ b/tests/asicworld/code_verilog_tutorial_always_example.v @@ -4,7 +4,7 @@ reg clk,reset,enable,q_in,data; always @ (posedge clk) if (reset) begin data <= 0; -end else if (enable) begin +end else if (enable) begin data <= q_in; end diff --git a/tests/asicworld/code_verilog_tutorial_bus_con.v b/tests/asicworld/code_verilog_tutorial_bus_con.v index b100c8136..7815f0469 100644 --- a/tests/asicworld/code_verilog_tutorial_bus_con.v +++ b/tests/asicworld/code_verilog_tutorial_bus_con.v @@ -2,7 +2,7 @@ module bus_con (a,b, y); input [3:0] a, b; output [7:0] y; wire [7:0] y; - + assign y = {a,b}; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_comment.v b/tests/asicworld/code_verilog_tutorial_comment.v index 1cc0eb424..62d5875c5 100644 --- a/tests/asicworld/code_verilog_tutorial_comment.v +++ b/tests/asicworld/code_verilog_tutorial_comment.v @@ -15,11 +15,11 @@ input ci; // Output ports output sum; output co; -// Data Types +// Data Types wire a; wire b; wire ci; wire sum; -wire co; +wire co; endmodule diff --git a/tests/asicworld/code_verilog_tutorial_counter.v b/tests/asicworld/code_verilog_tutorial_counter.v index 10ca00df4..6018d07f7 100644 --- a/tests/asicworld/code_verilog_tutorial_counter.v +++ b/tests/asicworld/code_verilog_tutorial_counter.v @@ -7,7 +7,7 @@ module counter (clk, reset, enable, count); input clk, reset, enable; output [3:0] count; -reg [3:0] count; +reg [3:0] count; always @ (posedge clk) if (reset == 1'b1) begin @@ -16,4 +16,4 @@ end else if ( enable == 1'b1) begin count <= count + 1; end -endmodule +endmodule diff --git a/tests/asicworld/code_verilog_tutorial_d_ff.v b/tests/asicworld/code_verilog_tutorial_d_ff.v index 7a4083605..ba18b708a 100644 --- a/tests/asicworld/code_verilog_tutorial_d_ff.v +++ b/tests/asicworld/code_verilog_tutorial_d_ff.v @@ -4,7 +4,7 @@ input d ,clk; output q, q_bar; wire d ,clk; reg q, q_bar; - + always @ (posedge clk) begin q <= d; diff --git a/tests/asicworld/code_verilog_tutorial_decoder.v b/tests/asicworld/code_verilog_tutorial_decoder.v index 5efdbd7e7..6cb4c7999 100644 --- a/tests/asicworld/code_verilog_tutorial_decoder.v +++ b/tests/asicworld/code_verilog_tutorial_decoder.v @@ -2,13 +2,13 @@ module decoder (in,out); input [2:0] in; output [7:0] out; wire [7:0] out; -assign out = (in == 3'b000 ) ? 8'b0000_0001 : -(in == 3'b001 ) ? 8'b0000_0010 : -(in == 3'b010 ) ? 8'b0000_0100 : -(in == 3'b011 ) ? 8'b0000_1000 : -(in == 3'b100 ) ? 8'b0001_0000 : -(in == 3'b101 ) ? 8'b0010_0000 : -(in == 3'b110 ) ? 8'b0100_0000 : +assign out = (in == 3'b000 ) ? 8'b0000_0001 : +(in == 3'b001 ) ? 8'b0000_0010 : +(in == 3'b010 ) ? 8'b0000_0100 : +(in == 3'b011 ) ? 8'b0000_1000 : +(in == 3'b100 ) ? 8'b0001_0000 : +(in == 3'b101 ) ? 8'b0010_0000 : +(in == 3'b110 ) ? 8'b0100_0000 : (in == 3'b111 ) ? 8'b1000_0000 : 8'h00; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_decoder_always.v b/tests/asicworld/code_verilog_tutorial_decoder_always.v index 4418ec700..5b31a2414 100644 --- a/tests/asicworld/code_verilog_tutorial_decoder_always.v +++ b/tests/asicworld/code_verilog_tutorial_decoder_always.v @@ -2,7 +2,7 @@ module decoder_always (in,out); input [2:0] in; output [7:0] out; reg [7:0] out; - + always @ (in) begin out = 0; @@ -16,5 +16,5 @@ begin 3'b111 : out = 8'b1000_0000; endcase end - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_escape_id.v b/tests/asicworld/code_verilog_tutorial_escape_id.v index 6c33da174..54eab1141 100644 --- a/tests/asicworld/code_verilog_tutorial_escape_id.v +++ b/tests/asicworld/code_verilog_tutorial_escape_id.v @@ -9,6 +9,6 @@ cl$k, // CLOCK input ); input d, cl$k, \reset* ; -output q, \q~ ; +output q, \q~ ; endmodule diff --git a/tests/asicworld/code_verilog_tutorial_explicit.v b/tests/asicworld/code_verilog_tutorial_explicit.v index 88427ff08..267db56ed 100644 --- a/tests/asicworld/code_verilog_tutorial_explicit.v +++ b/tests/asicworld/code_verilog_tutorial_explicit.v @@ -4,7 +4,7 @@ wire q; // Here q_bar is not connected // We can connect ports in any order -dff u0 ( +dff u0 ( .q (q), .d (d), .clk (clk), diff --git a/tests/asicworld/code_verilog_tutorial_first_counter.v b/tests/asicworld/code_verilog_tutorial_first_counter.v index d35d4aacc..c257bae64 100644 --- a/tests/asicworld/code_verilog_tutorial_first_counter.v +++ b/tests/asicworld/code_verilog_tutorial_first_counter.v @@ -19,7 +19,7 @@ input enable ; //-------------Output Ports---------------------------- output [3:0] counter_out ; //-------------Input ports Data Type------------------- -// By rule all the input ports should be wires +// By rule all the input ports should be wires wire clock ; wire reset ; wire enable ; diff --git a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v index 806e17736..bdca371e5 100644 --- a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v @@ -5,9 +5,9 @@ wire [3:0] counter_out; integer file; // Initialize all variables -initial begin +initial begin file = $fopen(`outfile); - $fdisplay (file, "time\t clk reset enable counter"); + $fdisplay (file, "time\t clk reset enable counter"); #5 reset = 1; // Assert the reset #10 reset = 0; // De-assert the reset #10 enable = 1; // Assert enable @@ -16,8 +16,8 @@ initial begin end always @(negedge clock) - $fdisplay (file, "%g\t %b %b %b %b", - $time, clock, reset, enable, counter_out); + $fdisplay (file, "%g\t %b %b %b %b", + $time, clock, reset, enable, counter_out); // Clock generator initial begin diff --git a/tests/asicworld/code_verilog_tutorial_flip_flop.v b/tests/asicworld/code_verilog_tutorial_flip_flop.v index ed2e88c2e..aeb784423 100644 --- a/tests/asicworld/code_verilog_tutorial_flip_flop.v +++ b/tests/asicworld/code_verilog_tutorial_flip_flop.v @@ -2,7 +2,7 @@ module flif_flop (clk,reset, q, d); input clk, reset, d; output q; reg q; - + always @ (posedge clk ) begin if (reset == 1) begin @@ -11,5 +11,5 @@ begin q <= d; end end - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full.v b/tests/asicworld/code_verilog_tutorial_fsm_full.v index fd2d559bb..0be754c97 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full.v @@ -20,13 +20,13 @@ input req_3 ; // Active high request from agent 3 output gnt_0 ; // Active high grant to agent 0 output gnt_1 ; // Active high grant to agent 1 output gnt_2 ; // Active high grant to agent 2 -output gnt_3 ; // Active high grant to agent +output gnt_3 ; // Active high grant to agent // Internal Variables reg gnt_0 ; // Active high grant to agent 0 reg gnt_1 ; // Active high grant to agent 1 reg gnt_2 ; // Active high grant to agent 2 -reg gnt_3 ; // Active high grant to agent +reg gnt_3 ; // Active high grant to agent parameter [2:0] IDLE = 3'b000; parameter [2:0] GNT0 = 3'b001; @@ -37,7 +37,7 @@ parameter [2:0] GNT3 = 3'b100; reg [2:0] state, next_state; always @ (state or req_0 or req_1 or req_2 or req_3) -begin +begin next_state = 0; case(state) IDLE : if (req_0 == 1'b1) begin @@ -50,7 +50,7 @@ begin next_state= GNT3; end else begin next_state = IDLE; - end + end GNT0 : if (req_0 == 1'b0) begin next_state = IDLE; end else begin diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v index a8e15568b..7c0e2d570 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v @@ -1,6 +1,6 @@ module testbench(); reg clock = 0 , reset ; -reg req_0 , req_1 , req_2 , req_3; +reg req_0 , req_1 , req_2 , req_3; wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ; integer file; @@ -29,7 +29,7 @@ initial begin end always @(negedge clock) - $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b", + $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b", $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); initial begin diff --git a/tests/asicworld/code_verilog_tutorial_multiply.v b/tests/asicworld/code_verilog_tutorial_multiply.v index 1912e1e26..bcab608cb 100644 --- a/tests/asicworld/code_verilog_tutorial_multiply.v +++ b/tests/asicworld/code_verilog_tutorial_multiply.v @@ -2,7 +2,7 @@ module muliply (a,product); input [3:0] a; output [4:0] product; wire [4:0] product; - + assign product = a << 1; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_mux_21.v b/tests/asicworld/code_verilog_tutorial_mux_21.v index a6a0d35eb..70f57205b 100644 --- a/tests/asicworld/code_verilog_tutorial_mux_21.v +++ b/tests/asicworld/code_verilog_tutorial_mux_21.v @@ -3,7 +3,7 @@ module mux_21 (a,b,sel,y); output y; input sel; wire y; - + assign y = (sel) ? b : a; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_n_out_primitive.v b/tests/asicworld/code_verilog_tutorial_n_out_primitive.v index 814385a45..b85738417 100644 --- a/tests/asicworld/code_verilog_tutorial_n_out_primitive.v +++ b/tests/asicworld/code_verilog_tutorial_n_out_primitive.v @@ -5,9 +5,9 @@ wire in; // one output Buffer gate buf u_buf0 (out,in); -// four output Buffer gate +// four output Buffer gate buf u_buf1 (out_0, out_1, out_2, out_3, in); -// three output Invertor gate +// three output Invertor gate not u_not0 (out_a, out_b, out_c, in); - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_parallel_if.v b/tests/asicworld/code_verilog_tutorial_parallel_if.v index 1dbe737eb..1cf8658b0 100644 --- a/tests/asicworld/code_verilog_tutorial_parallel_if.v +++ b/tests/asicworld/code_verilog_tutorial_parallel_if.v @@ -6,7 +6,7 @@ wire clk,reset,enable, up_en, down_en; always @ (posedge clk) // If reset is asserted if (reset == 1'b0) begin - counter <= 4'b0000; + counter <= 4'b0000; end else begin // If counter is enable and up count is mode if (enable == 1'b1 && up_en == 1'b1) begin @@ -15,7 +15,7 @@ end else begin // If counter is enable and down count is mode if (enable == 1'b1 && down_en == 1'b1) begin counter <= counter - 1'b1; - end -end + end +end endmodule diff --git a/tests/asicworld/code_verilog_tutorial_parity.v b/tests/asicworld/code_verilog_tutorial_parity.v index 764396c2f..27941f309 100644 --- a/tests/asicworld/code_verilog_tutorial_parity.v +++ b/tests/asicworld/code_verilog_tutorial_parity.v @@ -8,7 +8,7 @@ //----------------------------------------------------- module parity ( a , // First input -b , // Second input +b , // Second input c , // Third Input d , // Fourth Input y // Parity output @@ -38,4 +38,4 @@ xor u1 (out_1,c,d); xor u2 (y,out_0,out_1); -endmodule // End Of Module parity +endmodule // End Of Module parity diff --git a/tests/asicworld/code_verilog_tutorial_simple_if.v b/tests/asicworld/code_verilog_tutorial_simple_if.v index a68cc4a87..67fa8bcb1 100644 --- a/tests/asicworld/code_verilog_tutorial_simple_if.v +++ b/tests/asicworld/code_verilog_tutorial_simple_if.v @@ -6,6 +6,6 @@ wire enable,din; always @ (enable or din) if (enable) begin latch <= din; -end +end endmodule diff --git a/tests/asicworld/code_verilog_tutorial_tri_buf.v b/tests/asicworld/code_verilog_tutorial_tri_buf.v index a55b29caa..3df0d7009 100644 --- a/tests/asicworld/code_verilog_tutorial_tri_buf.v +++ b/tests/asicworld/code_verilog_tutorial_tri_buf.v @@ -3,7 +3,7 @@ module tri_buf (a,b,enable); output b; input enable; wire b; - + assign b = (enable) ? a : 1'bz; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_which_clock.v b/tests/asicworld/code_verilog_tutorial_which_clock.v index 418a2cfac..934015ac0 100644 --- a/tests/asicworld/code_verilog_tutorial_which_clock.v +++ b/tests/asicworld/code_verilog_tutorial_which_clock.v @@ -4,7 +4,7 @@ output q; reg q; always @ (posedge x or posedge y) - if (x) + if (x) q <= 1'b0; else q <= d; diff --git a/tests/bugpoint/procs.il b/tests/bugpoint/procs.il index cb9f7c8dd..e780dc7cd 100644 --- a/tests/bugpoint/procs.il +++ b/tests/bugpoint/procs.il @@ -13,11 +13,11 @@ module \ff_with_en_and_sync_reset switch \reset case 1'1 assign $0\q[0:0] 1'0 - case + case switch \enable case 1'1 assign $0\q[0:0] \d [0] - case + case end end sync posedge \clock @@ -29,11 +29,11 @@ module \ff_with_en_and_sync_reset switch \reset case 1'1 assign $0\q[1:1] 1'0 - case + case switch \enable case 1'1 assign $0\q[1:1] \d [1] - case + case end end sync posedge \clock diff --git a/tests/cxxrtl/test_value_fuzz.cc b/tests/cxxrtl/test_value_fuzz.cc index a77120136..500f48a7a 100644 --- a/tests/cxxrtl/test_value_fuzz.cc +++ b/tests/cxxrtl/test_value_fuzz.cc @@ -88,7 +88,7 @@ void test_binary_operation(Operation &op) } template -struct UnaryOperationWrapper : BinaryOperationBase +struct UnaryOperationWrapper : BinaryOperationBase { Operation &op; @@ -113,7 +113,7 @@ void test_unary_operation(Operation &op) test_binary_operation(wrapped); } -struct ShlTest : BinaryOperationBase +struct ShlTest : BinaryOperationBase { ShlTest() { @@ -138,7 +138,7 @@ struct ShlTest : BinaryOperationBase } } shl; -struct ShrTest : BinaryOperationBase +struct ShrTest : BinaryOperationBase { ShrTest() { @@ -163,7 +163,7 @@ struct ShrTest : BinaryOperationBase } } shr; -struct SshrTest : BinaryOperationBase +struct SshrTest : BinaryOperationBase { SshrTest() { @@ -189,7 +189,7 @@ struct SshrTest : BinaryOperationBase } } sshr; -struct AddTest : BinaryOperationBase +struct AddTest : BinaryOperationBase { AddTest() { @@ -209,7 +209,7 @@ struct AddTest : BinaryOperationBase } } add; -struct SubTest : BinaryOperationBase +struct SubTest : BinaryOperationBase { SubTest() { diff --git a/tests/functional/README.md b/tests/functional/README.md index 1459c3198..12f975929 100644 --- a/tests/functional/README.md +++ b/tests/functional/README.md @@ -6,12 +6,12 @@ Pytest options you might want: - `-v`: More progress indication. -- `--basetemp tmp`: Store test files (including vcd results) in tmp. +- `--basetemp tmp`: Store test files (including vcd results) in tmp. CAREFUL: contents of tmp will be deleted - `-k `: Run only tests that contain the pattern, e.g. `-k cxx` or `-k smt` or `-k demux` or `-k 'cxx[demux` - + - `-s`: Don't hide stdout/stderr from the test code. Custom options for functional backend tests: diff --git a/tests/functional/rkt_vcd.py b/tests/functional/rkt_vcd.py index 548a4ba74..8ce73273f 100644 --- a/tests/functional/rkt_vcd.py +++ b/tests/functional/rkt_vcd.py @@ -15,7 +15,7 @@ def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='to # Write the header f.write(f"$date\n {date}\n$end\n") f.write(f"$timescale {timescale} $end\n") - + # Declare signals f.write("$scope module gold $end\n") for signal_name, changes in signals.items(): @@ -23,17 +23,17 @@ def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='to f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") f.write("$upscope $end\n") f.write("$enddefinitions $end\n") - + # Collect all unique timestamps timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) - + # Write initial values f.write("#0\n") for signal_name, changes in signals.items(): for time, value in changes: if time == 0: f.write(f"{value} {signal_name}\n") - + # Write value changes for time in timestamps: if time != 0: diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py index 73e28b2b2..162ddf094 100644 --- a/tests/functional/smt_vcd.py +++ b/tests/functional/smt_vcd.py @@ -77,14 +77,14 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): smt_io.write(smt_io.unparse(expr)) if expr[0] == "declare-datatype": handle_datatype(expr) - + parser.finish() assert smt_io.check_sat() == 'sat' def set_step(inputs, step): # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4} # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input. - + mk_inputs_parts = [] for input_name, width in inputs.items(): value = rnd.getrandbits(width) # Generate a random number up to the maximum value for the bit size @@ -125,7 +125,7 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): for input_name, width in inputs.items(): value = smt_io.get(f'(gold_Inputs_{input_name} test_inputs_step_n{step})') value = hex_to_bin(value[1:]) - print(f" {input_name}: {value}") + print(f" {input_name}: {value}") signals[input_name].append((step, value)) for output_name, width in outputs.items(): value = smt_io.get(f'(gold_Outputs_{output_name} test_outputs_step_n{step})') @@ -145,7 +145,7 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): # Write the header f.write(f"$date\n {date}\n$end\n") f.write(f"$timescale {timescale} $end\n") - + # Declare signals f.write("$scope module gold $end\n") for signal_name, changes in signals.items(): @@ -153,17 +153,17 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") f.write("$upscope $end\n") f.write("$enddefinitions $end\n") - + # Collect all unique timestamps timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) - + # Write initial values f.write("#0\n") for signal_name, changes in signals.items(): for time, value in changes: if time == 0: f.write(f"{value} {signal_name}\n") - + # Write value changes for time in timestamps: if time != 0: diff --git a/tests/hana/hana_vlib.v b/tests/hana/hana_vlib.v index a8921bcfd..1b3d18191 100644 --- a/tests/hana/hana_vlib.v +++ b/tests/hana/hana_vlib.v @@ -1,4 +1,4 @@ -/* +/* Copyright (C) 2009-2010 Parvez Ahmad Written by Parvez Ahmad . @@ -45,7 +45,7 @@ module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ∈ endmodule - + module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ∈ @@ -63,7 +63,7 @@ module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = |in; endmodule - + module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = |in; @@ -82,7 +82,7 @@ module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~∈ endmodule - + module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~∈ @@ -100,7 +100,7 @@ module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~|in; endmodule - + module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~|in; @@ -119,7 +119,7 @@ module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ^in; endmodule - + module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ^in; @@ -138,7 +138,7 @@ module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~^in; endmodule - + module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~^in; @@ -156,7 +156,7 @@ always @(in or enable) 1'b1 : out = 2'b10; endcase end -endmodule +endmodule module DEC2 (input [1:0] in, input enable, output reg [3:0] out); @@ -171,7 +171,7 @@ always @(in or enable) 2'b11 : out = 4'b1000; endcase end -endmodule +endmodule module DEC3 (input [2:0] in, input enable, output reg [7:0] out); @@ -190,7 +190,7 @@ always @(in or enable) 3'b111 : out = 8'b10000000; endcase end -endmodule +endmodule module DEC4 (input [3:0] in, input enable, output reg [15:0] out); @@ -217,7 +217,7 @@ always @(in or enable) 4'b1111 : out = 16'b1000000000000000; endcase end -endmodule +endmodule module DEC5 (input [4:0] in, input enable, output reg [31:0] out); always @(in or enable) @@ -259,7 +259,7 @@ always @(in or enable) 5'b11111 : out = 32'b10000000000000000000000000000000; endcase end -endmodule +endmodule module DEC6 (input [5:0] in, input enable, output reg [63:0] out); @@ -335,7 +335,7 @@ always @(in or enable) 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase end -endmodule +endmodule module MUX2(input [1:0] in, input select, output reg out); @@ -345,7 +345,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule module MUX4(input [3:0] in, input [1:0] select, output reg out); @@ -357,7 +357,7 @@ always @( in or select) 2: out = in[2]; 3: out = in[3]; endcase -endmodule +endmodule module MUX8(input [7:0] in, input [2:0] select, output reg out); @@ -373,7 +373,7 @@ always @( in or select) 6: out = in[6]; 7: out = in[7]; endcase -endmodule +endmodule module MUX16(input [15:0] in, input [3:0] select, output reg out); @@ -396,7 +396,7 @@ always @( in or select) 14: out = in[14]; 15: out = in[15]; endcase -endmodule +endmodule module MUX32(input [31:0] in, input [4:0] select, output reg out); @@ -435,7 +435,7 @@ always @( in or select) 30: out = in[30]; 31: out = in[31]; endcase -endmodule +endmodule module MUX64(input [63:0] in, input [5:0] select, output reg out); @@ -506,7 +506,7 @@ always @( in or select) 62: out = in[62]; 63: out = in[63]; endcase -endmodule +endmodule module ADD1(input in1, in2, cin, output out, cout); @@ -514,41 +514,41 @@ assign {cout, out} = in1 + in2 + cin; endmodule -module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; @@ -561,41 +561,41 @@ assign {cout, out} = in1 - in2 - cin; endmodule -module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; @@ -651,7 +651,7 @@ assign rem = in1%in2; endmodule -module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -659,7 +659,7 @@ assign rem = in1%in2; endmodule -module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -667,7 +667,7 @@ assign rem = in1%in2; endmodule -module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -675,7 +675,7 @@ assign rem = in1%in2; endmodule -module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -683,7 +683,7 @@ assign rem = in1%in2; endmodule -module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -691,7 +691,7 @@ assign rem = in1%in2; endmodule -module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -711,7 +711,7 @@ always @(posedge clk or posedge reset) q <= 0; else q <= d; -endmodule +endmodule module SFF(input d, clk, set, output reg q); always @(posedge clk or posedge set) @@ -719,7 +719,7 @@ always @(posedge clk or posedge set) q <= 1; else q <= d; -endmodule +endmodule module RSFF(input d, clk, set, reset, output reg q); always @(posedge clk or posedge reset or posedge set) @@ -745,30 +745,30 @@ module LATCH(input d, enable, output reg q); always @( d or enable) if(enable) q <= d; -endmodule +endmodule module RLATCH(input d, reset, enable, output reg q); always @( d or enable or reset) if(enable) if(reset) q <= 0; - else + else q <= d; -endmodule +endmodule module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out); always @ (in, shift, val) begin if(shift) out = val; - else + else out = in; end endmodule -module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, +module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, input [SIZE-1:0] shift, input val, output reg [SIZE-1:0] out); @@ -776,58 +776,58 @@ always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, +module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, input [2:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, +module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, input [3:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, +module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, input [4:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, +module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, input [5:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, +module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, input [6:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out); @@ -841,7 +841,7 @@ end endmodule -module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, +module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, input [SIZE-1:0] shift, input val, output reg [SIZE-1:0] out); @@ -849,12 +849,12 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, +module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, input [2:0] shift, input val, output reg [SIZE-1:0] out); @@ -862,10 +862,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, +module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, input [3:0] shift, input val, output reg [SIZE-1:0] out); @@ -873,11 +873,11 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, +module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, input [4:0] shift, input val, output reg [SIZE-1:0] out); @@ -885,11 +885,11 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, +module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, input [5:0] shift, input val, output reg [SIZE-1:0] out); @@ -897,10 +897,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, +module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, input [6:0] shift, input val, output reg [SIZE-1:0] out); @@ -908,10 +908,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module CMP1 #(parameter SIZE = 1) (input in1, in2, +module CMP1 #(parameter SIZE = 1) (input in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -920,7 +920,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -928,17 +928,17 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, +module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -947,7 +947,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -955,16 +955,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, +module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -973,7 +973,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -981,16 +981,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, +module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -999,7 +999,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1007,16 +1007,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, +module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1025,7 +1025,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1033,16 +1033,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, +module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1051,7 +1051,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1059,16 +1059,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, +module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1077,7 +1077,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1085,12 +1085,12 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule diff --git a/tests/hana/test_intermout.v b/tests/hana/test_intermout.v index 88b91ee4d..649f78a0d 100644 --- a/tests/hana/test_intermout.v +++ b/tests/hana/test_intermout.v @@ -10,7 +10,7 @@ begin temp1 = a ^ b; temp2 = c ^ d; z = temp1 ^ temp2; -end +end endmodule @@ -24,7 +24,7 @@ always @ ( in1 or in2) out = in1; else out = in2; -endmodule +endmodule // test_intermout_always_comb_4_test.v module f3_test(a, b, c); @@ -46,9 +46,9 @@ output reg out; always @ (ctrl or in1 or in2) if(ctrl) out = in1 & in2; - else + else out = in1 | in2; -endmodule +endmodule // test_intermout_always_ff_3_test.v module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim); @@ -78,7 +78,7 @@ always @(posedge clk) is <= cs; assign ns = is; -endmodule +endmodule // test_intermout_always_ff_5_test.v module f7_FlipFlop(clock, cs, ns); @@ -91,9 +91,9 @@ always @(posedge clock) begin temp = cs; ns = temp; -end +end -endmodule +endmodule // test_intermout_always_ff_6_test.v module f8_inc(clock, counter); @@ -102,7 +102,7 @@ input clock; output reg [3:0] counter; always @(posedge clock) counter <= counter + 1; -endmodule +endmodule // test_intermout_always_ff_8_test.v module f9_NegEdgeClock(q, d, clk, reset); @@ -112,7 +112,7 @@ output reg q; always @(negedge clk or negedge reset) if(!reset) q <= 1'b0; - else + else q <= d; endmodule @@ -131,7 +131,7 @@ always @(posedge clock) counter <= counter + 1; else counter <= counter - 1; -endmodule +endmodule // test_intermout_always_latch_1_test.v module f11_test(en, in, out); @@ -142,7 +142,7 @@ output reg [2:0] out; always @ (en or in) if(en) out = in + 1; -endmodule +endmodule // test_intermout_bufrm_1_test.v module f12_test(input in, output out); @@ -364,20 +364,20 @@ endmodule // test_intermout_exprs_redop_test.v module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6); -input [1:0] A1; -input [1:0] A2; -input [1:0] A3; -input [1:0] A4; -input [1:0] A5; -input [1:0] A6; -output Y1, Y2, Y3, Y4, Y5, Y6; -//reg Y1, Y2, Y3, Y4, Y5, Y6; -assign Y1=&A1; //reduction AND -assign Y2=|A2; //reduction OR -assign Y3=~&A3; //reduction NAND -assign Y4=~|A4; //reduction NOR -assign Y5=^A5; //reduction XOR -assign Y6=~^A6; //reduction XNOR +input [1:0] A1; +input [1:0] A2; +input [1:0] A3; +input [1:0] A4; +input [1:0] A5; +input [1:0] A6; +output Y1, Y2, Y3, Y4, Y5, Y6; +//reg Y1, Y2, Y3, Y4, Y5, Y6; +assign Y1=&A1; //reduction AND +assign Y2=|A2; //reduction OR +assign Y3=~&A3; //reduction NAND +assign Y4=~|A4; //reduction NOR +assign Y5=^A5; //reduction XOR +assign Y6=~^A6; //reduction XNOR endmodule // test_intermout_exprs_sub_test.v diff --git a/tests/hana/test_parse2synthtrans.v b/tests/hana/test_parse2synthtrans.v index 19943ffb5..7185065fb 100644 --- a/tests/hana/test_parse2synthtrans.v +++ b/tests/hana/test_parse2synthtrans.v @@ -18,7 +18,7 @@ always @(clk or reset) begin d = d*d; if(b) e = d*d; - else + else e = d + d; end endmodule diff --git a/tests/hana/test_simulation_always.v b/tests/hana/test_simulation_always.v index 3ee75313a..0da8e43bd 100644 --- a/tests/hana/test_simulation_always.v +++ b/tests/hana/test_simulation_always.v @@ -4,7 +4,7 @@ module f1_test(input [1:0] in, output reg [1:0] out); always @(in) out = in; -endmodule +endmodule // test_simulation_always_17_test.v module f2_test(a, b, c, d, z); @@ -17,7 +17,7 @@ begin temp1 = a ^ b; temp2 = c ^ d; z = temp1 ^ temp2; -end +end endmodule @@ -31,7 +31,7 @@ always @ ( in1 or in2) out = in1; else out = in2; -endmodule +endmodule // test_simulation_always_19_test.v module f4_test(ctrl, in1, in2, out); @@ -42,16 +42,16 @@ output reg out; always @ (ctrl or in1 or in2) if(ctrl) out = in1 & in2; - else + else out = in1 | in2; -endmodule +endmodule // test_simulation_always_1_test.v module f5_test(input in, output reg out); always @(in) out = in; -endmodule +endmodule // test_simulation_always_20_test.v module f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim); @@ -81,7 +81,7 @@ always @(posedge clk) is <= cs; assign ns = is; -endmodule +endmodule // test_simulation_always_22_test.v module f8_inc(clock, counter); @@ -90,7 +90,7 @@ input clock; output reg [7:0] counter; always @(posedge clock) counter <= counter + 1; -endmodule +endmodule // test_simulation_always_23_test.v module f9_MyCounter (clock, preset, updown, presetdata, counter); @@ -106,7 +106,7 @@ always @(posedge clock) counter <= counter + 1; else counter <= counter - 1; -endmodule +endmodule // test_simulation_always_27_test.v module f10_FlipFlop(clock, cs, ns); @@ -119,9 +119,9 @@ always @(posedge clock) begin temp <= cs; ns <= temp; -end +end -endmodule +endmodule // test_simulation_always_29_test.v module f11_test(input in, output reg [1:0] out); diff --git a/tests/hana/test_simulation_decoder.v b/tests/hana/test_simulation_decoder.v index 2a102a903..311d425c8 100644 --- a/tests/hana/test_simulation_decoder.v +++ b/tests/hana/test_simulation_decoder.v @@ -45,7 +45,7 @@ always @(in ) 3'b110 : out = 8'b01000000; 3'b111 : out = 8'b10000000; endcase -endmodule +endmodule // test_simulation_decoder_5_test.v module f4_test (input [2:0] in, input enable, output reg [7:0] out); @@ -53,7 +53,7 @@ module f4_test (input [2:0] in, input enable, output reg [7:0] out); always @(in or enable ) if(!enable) out = 8'b00000000; - else + else case (in) 3'b000 : out = 8'b00000001; 3'b001 : out = 8'b00000010; @@ -64,7 +64,7 @@ always @(in or enable ) 3'b110 : out = 8'b01000000; 3'b111 : out = 8'b10000000; endcase -endmodule +endmodule // test_simulation_decoder_6_test.v module f5_test (input [3:0] in, input enable, output reg [15:0] out); @@ -92,7 +92,7 @@ always @(in or enable) 4'b1111 : out = 16'b1000000000000000; endcase end -endmodule +endmodule // test_simulation_decoder_7_test.v @@ -137,7 +137,7 @@ always @(in or enable) 5'b11111 : out = 32'b10000000000000000000000000000000; endcase end -endmodule +endmodule // test_simulation_decoder_8_test.v @@ -215,4 +215,4 @@ always @(in or enable) 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase end -endmodule +endmodule diff --git a/tests/hana/test_simulation_mux.v b/tests/hana/test_simulation_mux.v index 085387eff..6fc912893 100644 --- a/tests/hana/test_simulation_mux.v +++ b/tests/hana/test_simulation_mux.v @@ -31,7 +31,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule // test_simulation_mux_32_test.v module f3_test(input [31:0] in, input [4:0] select, output reg out); @@ -71,7 +71,7 @@ always @( in or select) 30: out = in[30]; 31: out = in[31]; endcase -endmodule +endmodule // test_simulation_mux_4_test.v @@ -84,7 +84,7 @@ always @( in or select) 2: out = in[2]; 3: out = in[3]; endcase -endmodule +endmodule // test_simulation_mux_64_test.v module f5_test(input [63:0] in, input [5:0] select, output reg out); @@ -156,7 +156,7 @@ always @( in or select) 62: out = in[62]; 63: out = in[63]; endcase -endmodule +endmodule // test_simulation_mux_8_test.v diff --git a/tests/hana/test_simulation_seq.v b/tests/hana/test_simulation_seq.v index eba4e88ea..d5069bb76 100644 --- a/tests/hana/test_simulation_seq.v +++ b/tests/hana/test_simulation_seq.v @@ -3,10 +3,10 @@ module f1_test(input in, input clk, output reg out); always @(posedge clk) out <= in; -endmodule +endmodule // test_simulation_seq_ff_2_test.v module f2_test(input in, input clk, output reg out); always @(negedge clk) out <= in; -endmodule +endmodule diff --git a/tests/hana/test_simulation_sop.v b/tests/hana/test_simulation_sop.v index 79870cf0c..9373ea085 100644 --- a/tests/hana/test_simulation_sop.v +++ b/tests/hana/test_simulation_sop.v @@ -7,7 +7,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule // test_simulation_sop_basic_11_test.v module f2_test(input [3:0] in, input [1:0] select, output reg out); @@ -19,7 +19,7 @@ always @( in or select) 2: out = in[2]; 3: out = in[3]; endcase -endmodule +endmodule // test_simulation_sop_basic_12_test.v module f3_test(input [7:0] in, input [2:0] select, output reg out); diff --git a/tests/hana/test_simulation_techmap.v b/tests/hana/test_simulation_techmap.v index 88e24d0e7..65dd88d86 100644 --- a/tests/hana/test_simulation_techmap.v +++ b/tests/hana/test_simulation_techmap.v @@ -17,7 +17,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule // test_simulation_techmap_mux_128_test.v module f4_test(input [127:0] in, input [6:0] select, output reg out); diff --git a/tests/hana/test_simulation_vlib.v b/tests/hana/test_simulation_vlib.v index cdf3c56db..49f612b80 100644 --- a/tests/hana/test_simulation_vlib.v +++ b/tests/hana/test_simulation_vlib.v @@ -44,14 +44,14 @@ AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out( AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out( synth_net_11)); BUF synth_BUF(.in(synth_net), .out(synth_net_0)); -BUF +BUF synth_BUF_0(.in(data), .out(synth_net_3)); BUF synth_BUF_1(.in(synth_net_8) , .out(tmp)); BUF synth_BUF_2(.in(tmp), .out(synth_net_9)); MUX2 synth_MUX(. in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6)); -MUX2 +MUX2 synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7 )); FF synth_FF(.d(synth_net_11), .clk(clk), .q(data)); diff --git a/tests/liberty/busdef.lib b/tests/liberty/busdef.lib index b5e3d50b9..10c45cd99 100644 --- a/tests/liberty/busdef.lib +++ b/tests/liberty/busdef.lib @@ -15,14 +15,14 @@ library(supergate) { technology (cmos); revision : 1.0; - + time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; - + current_unit : "1uA"; + capacitive_load_unit(1,ff); - + default_inout_pin_cap : 7.0; default_input_pin_cap : 7.0; default_output_pin_cap : 0.0; @@ -35,9 +35,9 @@ library(supergate) { nom_process : 1.0; nom_temperature : 25.0; nom_voltage : 1.2; - + delay_model : generic_cmos; - + type( IO_bus_3_to_0 ) { base_type : array ; data_type : bit ; diff --git a/tests/liberty/dff.lib b/tests/liberty/dff.lib index b5df36587..0f725fd9d 100644 --- a/tests/liberty/dff.lib +++ b/tests/liberty/dff.lib @@ -6,7 +6,7 @@ library(dff) { ff("IQ", "IQN") { next_state : "(D)"; clocked_on : (CLK); - } + } pin(D) { direction : input; } @@ -15,7 +15,7 @@ library(dff) { } pin(Q) { direction: output; - function : IQ; + function : IQ; } } diff --git a/tests/liberty/issue3498_bad.lib b/tests/liberty/issue3498_bad.lib index f85c4e19b..9f2a90295 100644 --- a/tests/liberty/issue3498_bad.lib +++ b/tests/liberty/issue3498_bad.lib @@ -1,8 +1,8 @@ -library(fake) { - cell(bugbad) { - bundle(X) { +library(fake) { + cell(bugbad) { + bundle(X) { members(x1, x2); - power_down_function : !a+b ; + power_down_function : !a+b ; } } } diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib index 4621194dd..d8cc1d91b 100644 --- a/tests/liberty/normal.lib +++ b/tests/liberty/normal.lib @@ -15,14 +15,14 @@ library(supergate) { technology (cmos); revision : 1.0; - + time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; - + current_unit : "1uA"; + capacitive_load_unit(1,ff); - + default_inout_pin_cap : 7.0; default_input_pin_cap : 7.0; default_output_pin_cap : 0.0; @@ -35,27 +35,27 @@ library(supergate) { nom_process : 1.0; nom_temperature : 25.0; nom_voltage : 1.2; - + delay_model : generic_cmos; - + /* Inverter */ cell (inv) { area : 1; pin(A) { direction : input; } - + pin(Y) { direction : output; function : "A'"; } } - + /* tri-state inverter */ cell (tri_inv) { area : 4; pin(A) { - direction : input; + direction : input; } pin(S) { direction : input; @@ -66,7 +66,7 @@ library(supergate) { three_State : "S'"; } } - + cell (buffer) { area : 5; pin(A) { @@ -76,8 +76,8 @@ library(supergate) { direction : output; function : "A"; } - } - + } + /* 2-input NAND gate */ cell (nand2) { area : 3; @@ -92,7 +92,7 @@ library(supergate) { function : "(A * B)'"; } } - + /* 2-input NOR gate */ cell (nor2) { area : 3; @@ -107,7 +107,7 @@ library(supergate) { function : "(A + B)'"; } } - + /* 2-input XOR */ cell (xor2) { area : 6; @@ -122,7 +122,7 @@ library(supergate) { function : "(A *B') + (A' * B)"; } } - + /* 2-input inverting MUX */ cell (imux2) { area : 5; @@ -134,13 +134,13 @@ library(supergate) { } pin(S) { direction : input; - } + } pin(Y) { direction: output; function : "( (A * S) + (B * S') )'"; } } - + /* D-type flip-flop with asynchronous reset and preset */ cell (dff) { area : 6; @@ -151,7 +151,7 @@ library(supergate) { preset : "PRESET"; clear_preset_var1 : L; clear_preset_var2 : L; - } + } pin(D) { direction : input; } @@ -172,7 +172,7 @@ library(supergate) { intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; - fall_resistance : 0; + fall_resistance : 0; related_pin : "CLK"; } timing () { @@ -186,7 +186,7 @@ library(supergate) { timing_sense : negative_unate; intrinsic_rise : 75; related_pin : "PRESET"; - } + } } pin(QN) { direction: output; @@ -196,7 +196,7 @@ library(supergate) { intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; - fall_resistance : 0; + fall_resistance : 0; related_pin : "CLK"; } timing () { @@ -210,8 +210,8 @@ library(supergate) { timing_sense : positive_unate; intrinsic_fall : 75; related_pin : "PRESET"; - } - } + } + } } /* Latch */ @@ -228,12 +228,12 @@ library(supergate) { pin(G) { direction : input; } - + pin(Q) { direction : output; function : "IQ"; internal_node : "Q"; - + timing() { timing_type : rising_edge; intrinsic_rise : 65; @@ -242,7 +242,7 @@ library(supergate) { fall_resistance : 0; related_pin : "G"; } - + timing() { timing_sense : positive_unate; intrinsic_rise : 65; @@ -252,12 +252,12 @@ library(supergate) { related_pin : "D"; } } - + pin(QN) { direction : output; function : "IQN"; internal_node : "QN"; - + timing() { timing_type : rising_edge; intrinsic_rise : 65; @@ -266,7 +266,7 @@ library(supergate) { fall_resistance : 0; related_pin : "G"; } - + timing() { timing_sense : negative_unate; intrinsic_rise : 65; @@ -289,7 +289,7 @@ library(supergate) { } pin(C) { direction : input; - } + } pin(Y) { direction: output; function : "((A * B) + C)'"; @@ -308,7 +308,7 @@ library(supergate) { } pin(C) { direction : input; - } + } pin(Y) { direction: output; function : "((A + B) * C)'"; @@ -327,11 +327,11 @@ library(supergate) { pin(C) { direction : output; function : "(A * B)"; - } + } pin(Y) { direction: output; function : "(A *B') + (A' * B)"; - } + } } /* full adder */ @@ -345,7 +345,7 @@ library(supergate) { } pin(CI) { direction : input; - } + } pin(CO) { direction : output; function : "(((A * B)+(B * CI))+(CI * A))"; @@ -353,7 +353,7 @@ library(supergate) { pin(Y) { direction: output; function : "((A^B)^CI)"; - } + } } } /* end */ diff --git a/tests/liberty/processdefs.lib b/tests/liberty/processdefs.lib index 37a6bbaf8..209ee148c 100644 --- a/tests/liberty/processdefs.lib +++ b/tests/liberty/processdefs.lib @@ -17,9 +17,9 @@ library(processdefs) { revision : 1.0; time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; + current_unit : "1uA"; capacitive_load_unit(1,ff); @@ -37,7 +37,7 @@ library(processdefs) { nom_voltage : 1.2; delay_model : generic_cmos; - + define_cell_area(bond_pads,pad_slots) input_voltage(cmos) { vil : 0.3 * VDD ; diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib index 6a7fa77cc..49b33d918 100644 --- a/tests/liberty/semicolextra.lib +++ b/tests/liberty/semicolextra.lib @@ -26,7 +26,7 @@ library(supergate) { "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \ "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); }; } - } + } pin(CK) { direction : input; diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib index a58bb7fe1..b18f14d9a 100644 --- a/tests/liberty/semicolmissing.lib +++ b/tests/liberty/semicolmissing.lib @@ -14,7 +14,7 @@ /* */ /********************************************/ -/* +/* semi colon is missing in full-adder specification some TSMC liberty files are formatted this way.. */ @@ -22,14 +22,14 @@ library(supergate) { technology (cmos); revision : 1.0; - + time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; - + current_unit : "1uA"; + capacitive_load_unit(1,ff); - + default_inout_pin_cap : 7.0; default_input_pin_cap : 7.0; default_output_pin_cap : 0.0; @@ -42,9 +42,9 @@ library(supergate) { nom_process : 1.0; nom_temperature : 25.0; nom_voltage : 1.2; - + delay_model : generic_cmos; - + /* full adder */ cell (fulladder) { area : 8 @@ -56,7 +56,7 @@ library(supergate) { } pin(CI) { direction : input - } + } pin(CO) { direction : output function : "(((A * B)+(B * CI))+(CI * A))" @@ -64,7 +64,7 @@ library(supergate) { pin(Y) { direction: output function : "((A^B)^CI)" - } + } } } /* end */ diff --git a/tests/liberty/small.v b/tests/liberty/small.v index bd94be4fc..89774881c 100644 --- a/tests/liberty/small.v +++ b/tests/liberty/small.v @@ -8,7 +8,7 @@ module small initial count = 0; -always @ (posedge clk) +always @ (posedge clk) begin count <= count + 1'b1; end diff --git a/tests/memlib/memlib_9b1B.txt b/tests/memlib/memlib_9b1B.txt index 4917aaf8b..53eed3250 100644 --- a/tests/memlib/memlib_9b1B.txt +++ b/tests/memlib/memlib_9b1B.txt @@ -3,7 +3,7 @@ ram block \RAM_9b1B { abits 7; widths 1 2 4 9 18 per_port; byte 9; - + ifdef INIT_NONE { option "INIT" "NONE" { init none; diff --git a/tests/memlib/memlib_9b1B.v b/tests/memlib/memlib_9b1B.v index 9a8246c9f..618e3a516 100644 --- a/tests/memlib/memlib_9b1B.v +++ b/tests/memlib/memlib_9b1B.v @@ -1,4 +1,4 @@ -module RAM_9b1B +module RAM_9b1B #( parameter INIT = 0, parameter OPTION_INIT = "UNDEFINED", diff --git a/tests/memlib/memlib_block_sp.v b/tests/memlib/memlib_block_sp.v index 1f7830137..63325604f 100644 --- a/tests/memlib/memlib_block_sp.v +++ b/tests/memlib/memlib_block_sp.v @@ -27,13 +27,13 @@ initial else if (OPTION_RDINIT == "ANY") PORT_A_RD_DATA = PORT_A_RD_INIT_VALUE; -localparam ARST_VALUE = +localparam ARST_VALUE = (OPTION_RDARST == "ZERO") ? 16'h0000 : (OPTION_RDARST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDARST == "ANY") ? PORT_A_RD_ARST_VALUE : 16'hxxxx; -localparam SRST_VALUE = +localparam SRST_VALUE = (OPTION_RDSRST == "ZERO") ? 16'h0000 : (OPTION_RDSRST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDSRST == "ANY") ? PORT_A_RD_SRST_VALUE : diff --git a/tests/memlib/memlib_block_sp_full.v b/tests/memlib/memlib_block_sp_full.v index 8ba32b9ed..c78c36990 100644 --- a/tests/memlib/memlib_block_sp_full.v +++ b/tests/memlib/memlib_block_sp_full.v @@ -28,13 +28,13 @@ initial else if (OPTION_RDINIT == "ANY") PORT_A_RD_DATA = PORT_A_RD_INIT_VALUE; -localparam ARST_VALUE = +localparam ARST_VALUE = (OPTION_RDARST == "ZERO") ? 16'h0000 : (OPTION_RDARST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDARST == "ANY") ? PORT_A_RD_ARST_VALUE : 16'hxxxx; -localparam SRST_VALUE = +localparam SRST_VALUE = (OPTION_RDSRST == "ZERO") ? 16'h0000 : (OPTION_RDSRST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDSRST == "ANY") ? PORT_A_RD_SRST_VALUE : diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v index 305339dd9..f134262f2 100644 --- a/tests/memories/issue00335.v +++ b/tests/memories/issue00335.v @@ -6,11 +6,11 @@ module ram2 #( parameter SIZE = 5 // Address size ) (input clk, input sel, - input we, - input [SIZE-1:0] adr, - input [63:0] dat_i, + input we, + input [SIZE-1:0] adr, + input [63:0] dat_i, output reg [63:0] dat_o); - + reg [63:0] mem [0:(1 << SIZE)-1]; integer i; @@ -19,7 +19,7 @@ module ram2 #( for (i = 0; i < (1<signed - + // Combine with unsigned offset assign result = sum_full + $signed({6'b0, unsigned_offset}); endmodule @@ -1218,17 +1218,17 @@ module top ( ); wire signed [5:0] extended_base; wire signed [6:0] offset_sum; - + // Conditional sign extension based on input - assign extended_base = extend_sign ? + assign extended_base = extend_sign ? {{1{base_val[4]}}, base_val} : // Sign extend {1'b0, base_val}; // Zero extend - + // Mix of signed and unsigned offsets - assign offset_sum = $signed({2'b0, pos_offset1}) + - $signed({2'b0, pos_offset2}) + + assign offset_sum = $signed({2'b0, pos_offset1}) + + $signed({2'b0, pos_offset2}) + {{2{signed_offset[3]}}, signed_offset}; - + assign result = extended_base + offset_sum; endmodule EOF diff --git a/tests/pass-fuzzing.md b/tests/pass-fuzzing.md index 993f36078..99bf51c08 100644 --- a/tests/pass-fuzzing.md +++ b/tests/pass-fuzzing.md @@ -53,7 +53,7 @@ index 9c361294d..c9a98f74c 100644 +++ b/Makefile @@ -238,7 +238,7 @@ LTOFLAGS := $(GCC_LTO) - + ifeq ($(CONFIG),clang) -CXX = clang++ +CXX = $(HOME)/AFLplusplus/afl-c++ @@ -76,7 +76,7 @@ Generate some initial testcases using Grammar-Mutator: (cd $HOME/Grammar-Mutator; rm -rf seeds trees; ./grammar_generator-rtlil 100 1000 ./seeds ./trees) ``` -Now run AFL++. +Now run AFL++. ``` (cd $HOME/Grammar-Mutator; \ AFL_CUSTOM_MUTATOR_LIBRARY=./libgrammarmutator-rtlil.so \ diff --git a/tests/sat/grom.ys b/tests/sat/grom.ys index da0f3b620..b86822b30 100644 --- a/tests/sat/grom.ys +++ b/tests/sat/grom.ys @@ -1,5 +1,5 @@ read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v; -prep -top grom_computer; +prep -top grom_computer; sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80 sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp diff --git a/tests/sat/grom_cpu.v b/tests/sat/grom_cpu.v index 914c0f56c..0a29ffdb6 100644 --- a/tests/sat/grom_cpu.v +++ b/tests/sat/grom_cpu.v @@ -173,12 +173,12 @@ module grom_cpu( 3'b011 : begin RESULT_REG <= IR[1:0]; // result in REG - // CMP and TEST are not storing result + // CMP and TEST are not storing result state <= IR[3] ? STATE_FETCH_PREP : STATE_ALU_RESULT_WAIT; // CMP and TEST are having first input R0, for INC and DEC is REG - alu_a <= IR[3] ? R[0] : R[IR[1:0]]; + alu_a <= IR[3] ? R[0] : R[IR[1:0]]; // CMP and TEST are having second input REG, for INC and DEC is 1 - alu_b <= IR[3] ? R[IR[1:0]] : 8'b00000001; + alu_b <= IR[3] ? R[IR[1:0]] : 8'b00000001; case(IR[3:2]) 2'b00 : begin diff --git a/tests/sdc/alu_sub.sdc b/tests/sdc/alu_sub.sdc index f298d20bc..e50f572a5 100644 --- a/tests/sdc/alu_sub.sdc +++ b/tests/sdc/alu_sub.sdc @@ -7,7 +7,7 @@ current_design wrapper # Timing Constraints ############################################################################### create_clock -name this_clk -period 1.0000 [get_ports {clk}] -create_clock -name that_clk -period 2.0000 +create_clock -name that_clk -period 2.0000 create_clock -name another_clk -period 2.0000 \ [list [get_ports {A[0]}]\ [get_ports {A[1]}]\ diff --git a/tests/sim/generate_mk.py b/tests/sim/generate_mk.py index 57138762d..47b22971a 100644 --- a/tests/sim/generate_mk.py +++ b/tests/sim/generate_mk.py @@ -11,7 +11,7 @@ from pathlib import Path print("Generate FST for sim models") for name in Path("tb").rglob("tb*.v"): - test_name = name.stem + test_name = name.stem print(f"Test {test_name}") verilog_name = f"{test_name[3:]}.v" diff --git a/tests/sim/tb/tb_adff.v b/tests/sim/tb/tb_adff.v index f1bc3547e..e6a9294e2 100644 --- a/tests/sim/tb/tb_adff.v +++ b/tests/sim/tb/tb_adff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_adff(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_adffe.v b/tests/sim/tb/tb_adffe.v index bb23f963d..f1874e07d 100644 --- a/tests/sim/tb/tb_adffe.v +++ b/tests/sim/tb/tb_adffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_adffe(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_adlatch.v b/tests/sim/tb/tb_adlatch.v index 59dd498d2..a98d3ff52 100644 --- a/tests/sim/tb/tb_adlatch.v +++ b/tests/sim/tb/tb_adlatch.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_adlatch(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_aldff.v b/tests/sim/tb/tb_aldff.v index 0591c8b3c..f8bc6521e 100644 --- a/tests/sim/tb/tb_aldff.v +++ b/tests/sim/tb/tb_aldff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_aldff(); reg clk = 0; reg aload = 0; diff --git a/tests/sim/tb/tb_aldffe.v b/tests/sim/tb/tb_aldffe.v index c3cb57f4e..d3caa4e4f 100644 --- a/tests/sim/tb/tb_aldffe.v +++ b/tests/sim/tb/tb_aldffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_aldffe(); reg clk = 0; reg aload = 0; diff --git a/tests/sim/tb/tb_dff.v b/tests/sim/tb/tb_dff.v index aa41d1c6c..129b1da38 100644 --- a/tests/sim/tb/tb_dff.v +++ b/tests/sim/tb/tb_dff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dff(); reg clk = 0; reg d = 0; diff --git a/tests/sim/tb/tb_dffe.v b/tests/sim/tb/tb_dffe.v index 4e262b928..8357cdf8b 100644 --- a/tests/sim/tb/tb_dffe.v +++ b/tests/sim/tb/tb_dffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dffe(); reg clk = 0; reg en = 0; diff --git a/tests/sim/tb/tb_dffsr.v b/tests/sim/tb/tb_dffsr.v index 6ecb85d67..0199a894a 100644 --- a/tests/sim/tb/tb_dffsr.v +++ b/tests/sim/tb/tb_dffsr.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dffsr(); reg clk = 0; reg d = 0; diff --git a/tests/sim/tb/tb_dlatch.v b/tests/sim/tb/tb_dlatch.v index aea6cb0a3..ebb4ca36a 100644 --- a/tests/sim/tb/tb_dlatch.v +++ b/tests/sim/tb/tb_dlatch.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dlatch(); reg clk = 0; reg en = 0; diff --git a/tests/sim/tb/tb_dlatchsr.v b/tests/sim/tb/tb_dlatchsr.v index 0105d3288..b48b09b60 100644 --- a/tests/sim/tb/tb_dlatchsr.v +++ b/tests/sim/tb/tb_dlatchsr.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dlatchsr(); reg d = 0; reg set = 0; diff --git a/tests/sim/tb/tb_sdff.v b/tests/sim/tb/tb_sdff.v index f8e2a1c9d..de668b362 100644 --- a/tests/sim/tb/tb_sdff.v +++ b/tests/sim/tb/tb_sdff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_sdff(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_sdffce.v b/tests/sim/tb/tb_sdffce.v index 1c9952806..8bfd35d94 100644 --- a/tests/sim/tb/tb_sdffce.v +++ b/tests/sim/tb/tb_sdffce.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_sdffce(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_sdffe.v b/tests/sim/tb/tb_sdffe.v index 36072f93d..869028c2b 100644 --- a/tests/sim/tb/tb_sdffe.v +++ b/tests/sim/tb/tb_sdffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_sdffe(); reg clk = 0; reg rst = 0; diff --git a/tests/svtypes/struct_simple.sv b/tests/svtypes/struct_simple.sv index c74289cc3..c9a833549 100644 --- a/tests/svtypes/struct_simple.sv +++ b/tests/svtypes/struct_simple.sv @@ -8,7 +8,7 @@ module top; logic x, y; } s; - struct packed signed { + struct packed signed { integer a; logic[15:0] b; logic[7:0] c; diff --git a/tests/techmap/dfflibmap_dffn_dffe.lib b/tests/techmap/dfflibmap_dffn_dffe.lib index 832edee67..2d79373a2 100644 --- a/tests/techmap/dfflibmap_dffn_dffe.lib +++ b/tests/techmap/dfflibmap_dffn_dffe.lib @@ -4,7 +4,7 @@ library(test) { ff("IQ", "IQN") { next_state : "D"; clocked_on : "!CLK"; - } + } pin(D) { direction : input; } @@ -18,7 +18,7 @@ library(test) { pin(QN) { direction: output; function : "IQN"; - } + } } cell (dffe) { area : 6; diff --git a/tests/various/bug1531.ys b/tests/various/bug1531.ys index 542223030..f91ba1dee 100644 --- a/tests/various/bug1531.ys +++ b/tests/various/bug1531.ys @@ -6,7 +6,7 @@ module top (y, clk, w); always @(posedge clk) // If the constant below is set to 2'b00, the correct output is generated. // vvvv - for (i = 1'b0; i < 2'b01; i = i + 2'b01) + for (i = 1'b0; i < 2'b01; i = i + 2'b01) y <= w || i[1:1]; endmodule EOT diff --git a/tests/various/bug1745.ys b/tests/various/bug1745.ys index 2e5b8c2d4..b2aa610f1 100644 --- a/tests/various/bug1745.ys +++ b/tests/various/bug1745.ys @@ -3,6 +3,6 @@ read_verilog <