Remove trailing whitespaces

tests/verific/blackbox.ys

@@ -4,7 +4,7 @@ parameter PATH = "DEFAULT";
 always @(posedge clk) begin
     if (PATH=="DEFAULT")
 		c <= a;
-	else 
+	else
 		c <= b;
 end
 

tests/verific/blackbox_ql.ys

@@ -1,4 +1,4 @@
-verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v 
+verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
 
 verific -sv <<EOF
 module top (
@@ -13,7 +13,7 @@ module top (
     input  wire [2:0] output_select,
     input  wire       register_inputs
 );
-	
+
 // module instantiation
 QL_DSP2_MULT_REGIN_REGOUT #(
     .MODE_BITS(80'h1232324)

tests/verific/bounds.vhd

@@ -75,7 +75,7 @@ entity test is
         -- NATURAL type
         natural_in : in NATURAL;
         natural_out : out NATURAL;
- 
+
         -- POSITIVE type
         positive_in : in POSITIVE;
         positive_out : out POSITIVE

tests/verific/case.sv

@@ -6,15 +6,15 @@ module top (
 	always @ (posedge clk)
 	begin
 		case (currentstate)
-			5'd1,5'd2, 5'd3: 
-				begin 
+			5'd1,5'd2, 5'd3:
+				begin
 					o <= 2'b01;
-				end	
+				end
 			5'd4:
 			  	begin
 					o <= 2'b10;
 				end
-			5'd5,5'd6,5'd7: 
+			5'd5,5'd6,5'd7:
 				begin
 					o <= 2'b11;
 				end

tests/verific/case.ys

@@ -1,12 +1,12 @@
 verific -cfg db_abstract_case_statement_synthesis 0
 read -sv case.sv
-verific -import top 
+verific -import top
 prep
 rename top gold
 
 verific -cfg db_abstract_case_statement_synthesis 1
 read -sv case.sv
-verific -import top 
+verific -import top
 prep
 rename top gate
 

tests/verific/ext_ramnet_err.sv

@@ -8,6 +8,6 @@ endmodule
 module top (input clk, input [3:0] addr, output [7:0] data, input [3:0] f_addr, input [7:0] f_data);
     sub_rom u_sub_rom (clk, addr, data);
 
-    always @(posedge clk) 
+    always @(posedge clk)
         assume(u_sub_rom.mem[f_addr] == f_data);
 endmodule

tests/verific/range_case.ys

@@ -1,12 +1,12 @@
 verific -cfg db_abstract_case_statement_synthesis 0
 read -sv range_case.sv
-verific -import top 
+verific -import top
 proc
 rename top gold
 
 verific -cfg db_abstract_case_statement_synthesis 1
 read -sv range_case.sv
-verific -import top 
+verific -import top
 proc
 rename top gate
 

tests/verific/rom_case.ys

@@ -47,7 +47,7 @@ architecture rtl of rom_example is
 	attribute rom_style : string;
 	attribute rom_style of data : signal is "block";
 begin
-	
+
 	p_rom : process(clk)
 	begin
 		if rising_edge(clk) then
@@ -63,7 +63,7 @@ begin
 			end case;
 		end if;
 	end process p_rom;
-	
+
 end architecture rtl;
 EOF
 hierarchy -top rom_example