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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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2
tests/various/check_4.ys
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@ -12,7 +12,7 @@ module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
wire arst = !data[0];
always @(posedge arst, posedge clk) begin
if (arst)
if (arst)
data <= 4'hx;
else
data <= mem[addr];