3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-05 15:06:11 +00:00

Remove trailing whitespaces

This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions

View file

@ -6,11 +6,11 @@ module ram2 #(
parameter SIZE = 5 // Address size
) (input clk,
input sel,
input we,
input [SIZE-1:0] adr,
input [63:0] dat_i,
input we,
input [SIZE-1:0] adr,
input [63:0] dat_i,
output reg [63:0] dat_o);
reg [63:0] mem [0:(1 << SIZE)-1];
integer i;
@ -19,7 +19,7 @@ module ram2 #(
for (i = 0; i < (1<<SIZE) - 1; i = i + 1)
mem[i] <= 0;
end
always @(posedge clk)
if (sel) begin
if (~we)