mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-29 20:18:53 +00:00
Code Activity

Remove trailing whitespaces

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/asicworld/code_verilog_tutorial_parity.v
View file

@ -8,7 +8,7 @@
//-----------------------------------------------------
module parity (
a , // First input
b , // Second input
b , // Second input
c , // Third Input
d , // Fourth Input
y // Parity output
@ -38,4 +38,4 @@ xor u1 (out_1,c,d);
xor u2 (y,out_0,out_1);
endmodule // End Of Module parity
endmodule // End Of Module parity