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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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4
tests/asicworld/code_verilog_tutorial_counter.v
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@ -7,7 +7,7 @@
module counter (clk, reset, enable, count);
input clk, reset, enable;
output [3:0] count;
reg [3:0] count;
reg [3:0] count;
always @ (posedge clk)
if (reset == 1'b1) begin
@ -16,4 +16,4 @@ end else if ( enable == 1'b1) begin
count <= count + 1;
end
endmodule
endmodule