mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-03 22:16:09 +00:00
Remove trailing whitespaces
This commit is contained in:
parent
48a3dcc02a
commit
a689342207
317 changed files with 3136 additions and 3136 deletions
|
|
@ -6,19 +6,19 @@
|
|||
|
||||
module GrayCounter
|
||||
#(parameter COUNTER_WIDTH = 4)
|
||||
|
||||
|
||||
(output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
|
||||
|
||||
|
||||
input wire Enable_in, //Count enable.
|
||||
input wire Clear_in, //Count reset.
|
||||
|
||||
|
||||
input wire Clk);
|
||||
|
||||
/////////Internal connections & variables///////
|
||||
reg [COUNTER_WIDTH-1:0] BinaryCount;
|
||||
|
||||
/////////Code///////////////////////
|
||||
|
||||
|
||||
always @ (posedge Clk)
|
||||
if (Clear_in) begin
|
||||
BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
|
||||
|
|
@ -29,5 +29,5 @@ module GrayCounter
|
|||
GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
|
||||
BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue