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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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4
tests/arch/quicklogic/qlf_k6n10f/dffs.ys
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@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dff # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre
select -assert-none t:sdffsre %% t:* %D
select -assert-none t:sdffsre %% t:* %D
design -load read
hierarchy -top my_dffe
@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre
select -assert-none t:sdffsre %% t:* %D
select -assert-none t:sdffsre %% t:* %D

4
tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
View file

@ -46,7 +46,7 @@ initial begin
end
`MEM_TEST_VECTOR
end
@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
always @(posedge clk) begin
if (i < VECTORLEN-1) begin
if (i > 0) begin
if($past(rce_a))
if($past(rce_a))
assert(rq_a == rq_a_e);
if($past(rce_b))
assert(rq_b == rq_b_e);

2
tests/arch/quicklogic/qlf_k6n10f/meminit.v
View file

@ -31,7 +31,7 @@ always @(posedge clk) begin
read_addr <= counter;
read_val <= mem[counter];
end else begin
did_read <= 1'b0;
did_read <= 1'b0;
end
if (!done)