Remove trailing whitespaces

tests/arch/ecp5/bug1598.ys

@@ -3,13 +3,13 @@ module led_blink (
         input clk,
         output ledc
     );
- 
+
     reg [6:0] led_counter = 0;
     always @( posedge clk ) begin
             led_counter <= led_counter + 1;
     end
     assign ledc = !led_counter[ 6:3 ];
- 
+
 endmodule
 EOT
 proc

tests/arch/ecp5/memories.ys

@@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp
 hierarchy -top sync_ram_tdp
 synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp
-select -assert-count 1 t:DP16KD 
+select -assert-count 1 t:DP16KD
 select -assert-none t:LUT4

tests/arch/ecp5/shifter.ys

@@ -5,6 +5,6 @@ flatten
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
- 
+
 select -assert-count 8 t:TRELLIS_FF
 select -assert-none t:TRELLIS_FF %% t:* %D