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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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2
tests/arch/analogdevices/asym_ram_sdp_read_wider.v
View file

@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;

8
tests/arch/analogdevices/attributes_test.ys
View file

@ -4,7 +4,7 @@ hierarchy -top block_ram
synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
# select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive.
# Check that distributed memory without parameters is not modified
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -13,7 +13,7 @@ synth_analogdevices -top distributed_ram -noiopad
cd distributed_ram # Constrain all select calls below inside the top module
select -assert-count 8 t:RAMS64X1
select -assert-count 8 t:FFRE
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -22,7 +22,7 @@ synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 64 t:RAMS64X1
select -assert-count 4 t:FFRE
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -30,7 +30,7 @@ setattr -set logic_block 1 block_ram/m:*
synth_analogdevices -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 0 t:RBRAM2
# Set ram_style block to a distributed memory; will be implemented as blockram
design -reset
read_verilog ../common/memory_attributes/attributes_test.v

4
tests/arch/analogdevices/blockram.ys
View file

@ -54,7 +54,7 @@ select -assert-count 1 t:RBRAM2
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp
@ -62,7 +62,7 @@ select -assert-count 1 t:RBRAM2
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set logic_block 1 m:memory
synth_analogdevices -top sync_ram_sdp -noiopad
cd sync_ram_sdp

6
tests/arch/analogdevices/bug1598.ys
View file

@ -3,14 +3,14 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices
equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices

4
tests/arch/analogdevices/dsp_abc9.ys
View file

@ -17,7 +17,7 @@ module top(input signed [24:0] A, input signed [17:0] B, output [47:0] P);
assign P = A * B;
endmodule
EOT
synth_analogdevices
synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
opt -full -fine
select -assert-count 2 t:$mul
@ -34,7 +34,7 @@ EOT
async2sync
techmap -map +/analogdevices/dsp_map.v
verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1
synth_analogdevices
synth_analogdevices
techmap -autoproc -wb -map +/analogdevices/cells_sim.v
opt -full -fine
select -assert-count 0 t:* t:$assert %d

2
tests/arch/common/blockram.v
View file

@ -233,7 +233,7 @@ endmodule // double_sync_ram_sdp
module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
(input wire clk_a, clk_b,
(input wire clk_a, clk_b,
input wire write_enable_a, write_enable_b,
input wire read_enable_a, read_enable_b,
input wire [DATA_WIDTH-1:0] write_data_a, write_data_b,

2
tests/arch/common/fsm.v
View file

@ -19,7 +19,7 @@
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end
end
else
case(state)
IDLE : if (req_0 == 1'b1) begin

2
tests/arch/common/shifter.v
View file

@ -13,5 +13,5 @@ module top(out, clk, in);
begin
out <= out >> 1;
out[7] <= in;
end
end
endmodule

4
tests/arch/ecp5/bug1598.ys
View file

@ -3,13 +3,13 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc

2
tests/arch/ecp5/memories.ys
View file

@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp
hierarchy -top sync_ram_tdp
synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp
select -assert-count 1 t:DP16KD
select -assert-count 1 t:DP16KD
select -assert-none t:LUT4

2
tests/arch/ecp5/shifter.ys
View file

@ -5,6 +5,6 @@ flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D

4
tests/arch/ice40/bug1598.ys
View file

@ -3,13 +3,13 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc

8
tests/arch/ice40/bug1626.ys
View file

@ -182,20 +182,20 @@ module \ahb_async_sram_halfwidth
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
case 1'1
case
case
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
switch \ahbls_hready
case 1'1
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
switch \ahbls_htrans [1]
case 1'1
case
case
end
case
case
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
case 1'1
case
case
end
end
end

6
tests/arch/ice40/ice40_dsp_const.ys
View file

@ -75,7 +75,7 @@ EOT
techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
async2sync
equiv_make top ref equiv
select -assert-any -module equiv t:$equiv
equiv_induct
equiv_make top ref equiv
select -assert-any -module equiv t:$equiv
equiv_induct
equiv_status -assert

2
tests/arch/ice40/spram.v
View file

@ -6,7 +6,7 @@ parameter SKIP_RDEN = 1;
input clk;
input write_enable, read_enable;
input [DATA_WIDTH - 1 : 0] write_data;
input [ADDR_WIDTH - 1 : 0] addr;
input [ADDR_WIDTH - 1 : 0] addr;
output [DATA_WIDTH - 1 : 0] read_data;
(* ram_style = "huge" *)

6
tests/arch/microchip/dff.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

6
tests/arch/microchip/dff_opt.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

8
tests/arch/microchip/dsp.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -120,7 +120,7 @@ output reg cout;
input [n:0] a;
input [n:0] b;
input [n-1:0] c;
always @(*)
always @(*)
begin
{cout,out} = a * b + c;
end

6
tests/arch/microchip/mult.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

8
tests/arch/microchip/ram_SDP.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -27,7 +27,7 @@ output reg [d_width-1:0] q;
reg [d_width-1:0] mem [mem_depth-1:0];
always @(posedge clk) begin
if (we) begin
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];

8
tests/arch/microchip/ram_TDP.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -28,7 +28,7 @@ reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
always @ (posedge clka)
begin
addra_reg <= addra;
if(wea) begin
mem[addra] <= dataina;
qa <= dataina;

6
tests/arch/microchip/reduce.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

6
tests/arch/microchip/simple_ram.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

8
tests/arch/microchip/uram_ar.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -28,7 +28,7 @@ reg [d_width-1:0] mem [mem_depth-1:0];
assign q = mem[waddr];
always @(posedge clk) begin
if (we)
if (we)
mem[waddr] <= data;
end

8
tests/arch/microchip/uram_sr.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -32,7 +32,7 @@ module uram_sr(clk, wr, raddr, din, waddr, dout);
end
always@(posedge clk) begin
raddr_reg <= raddr;
raddr_reg <= raddr;
if(wr)
mem[waddr]<= din;
end

6
tests/arch/microchip/widemux.ys
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

2
tests/arch/nanoxplore/meminit.v
View file

@ -31,7 +31,7 @@ always @(posedge clk) begin
read_addr <= counter;
read_val <= mem[counter];
end else begin
did_read <= 1'b0;
did_read <= 1'b0;
end
if (!done)

6
tests/arch/nanoxplore/meminit.ys
View file

@ -3,7 +3,7 @@ chparam -set DEPTH_LOG2 5 -set WIDTH 36
prep
opt_dff
prep -rdff
synth_nanoxplore
synth_nanoxplore
clean_zerowidth
select -assert-none t:$mem_v2 t:$mem
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@ -18,7 +18,7 @@ chparam -set DEPTH_LOG2 6 -set WIDTH 18
prep
opt_dff
prep -rdff
synth_nanoxplore
synth_nanoxplore
clean_zerowidth
select -assert-none t:$mem_v2 t:$mem
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v
@ -34,7 +34,7 @@ chparam -set DEPTH_LOG2 8 -set WIDTH 18
prep
opt_dff
prep -rdff
synth_nanoxplore
synth_nanoxplore
clean_zerowidth
select -assert-none t:$mem_v2 t:$mem
read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v

4
tests/arch/quicklogic/qlf_k6n10f/dffs.ys
View file

@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dff # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre
select -assert-none t:sdffsre %% t:* %D
select -assert-none t:sdffsre %% t:* %D
design -load read
hierarchy -top my_dffe
@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd my_dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:sdffsre
select -assert-none t:sdffsre %% t:* %D
select -assert-none t:sdffsre %% t:* %D

4
tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
View file

@ -46,7 +46,7 @@ initial begin
end
`MEM_TEST_VECTOR
end
@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i];
always @(posedge clk) begin
if (i < VECTORLEN-1) begin
if (i > 0) begin
if($past(rce_a))
if($past(rce_a))
assert(rq_a == rq_a_e);
if($past(rce_b))
assert(rq_b == rq_b_e);

2
tests/arch/quicklogic/qlf_k6n10f/meminit.v
View file

@ -31,7 +31,7 @@ always @(posedge clk) begin
read_addr <= counter;
read_val <= mem[counter];
end else begin
did_read <= 1'b0;
did_read <= 1'b0;
end
if (!done)

2
tests/arch/xilinx/asym_ram_sdp_read_wider.v
View file

@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA,
parameter WIDTHA = 4;
parameter SIZEA = 1024;
parameter ADDRWIDTHA = 10;
parameter WIDTHB = 16;
parameter SIZEB = 256;
parameter ADDRWIDTHB = 8;

8
tests/arch/xilinx/attributes_test.ys
View file

@ -4,7 +4,7 @@ hierarchy -top block_ram
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1
# Check that distributed memory without parameters is not modified
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -12,7 +12,7 @@ hierarchy -top distributed_ram
synth_xilinx -top distributed_ram -noiopad
cd distributed_ram # Constrain all select calls below inside the top module
select -assert-count 1 t:RAM32M
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -20,7 +20,7 @@ setattr -set ram_style "distributed" block_ram/m:*
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 16 t:RAM256X1S
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
@ -28,7 +28,7 @@ setattr -set logic_block 1 block_ram/m:*
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 0 t:RAMB18E1
# Set ram_style block to a distributed memory; will be implemented as blockram
design -reset
read_verilog ../common/memory_attributes/attributes_test.v

4
tests/arch/xilinx/blockram.ys
View file

@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
synth_xilinx -top sync_ram_sdp -noiopad
cd sync_ram_sdp
@ -58,7 +58,7 @@ select -assert-count 1 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set logic_block 1 m:memory
synth_xilinx -top sync_ram_sdp -noiopad
cd sync_ram_sdp

4
tests/arch/xilinx/bug1598.ys
View file

@ -3,13 +3,13 @@ module led_blink (
input clk,
output ledc
);
reg [6:0] led_counter = 0;
always @( posedge clk ) begin
led_counter <= led_counter + 1;
end
assign ledc = !led_counter[ 6:3 ];
endmodule
EOT
proc

2
tests/arch/xilinx/xilinx_srl.v
View file

@ -34,7 +34,7 @@ parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
if (E)
if (E)
r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule