mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-01 13:08:54 +00:00
Code Activity

Remove trailing whitespaces

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
Download patch file Download diff file Expand all files Collapse all files

24
techlibs/gowin/cells_sim.v
View file

@ -25,7 +25,7 @@ module LUT3(output F, input I0, I1, I2);
(I0 => F) = (1054, 1486);
(I1 => F) = (867, 1184);
(I2 => F) = (555, 902);
endspecify
endspecify
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
@ -39,7 +39,7 @@ module LUT4(output F, input I0, I1, I2, I3);
(I1 => F) = (1053, 1583);
(I2 => F) = (867, 1184);
(I3 => F) = (555, 902);
endspecify
endspecify
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
@ -54,7 +54,7 @@ module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);
(I2 => F) = (995, 1371);
(I3 => F) = (808, 1116);
(M0 => F) = (486, 680);
endspecify
endspecify
endmodule
(* abc9_lut=4 *)
@ -66,7 +66,7 @@ module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);
(I3 => F) = (808 + 136, 1116 + 255);
(M0 => F) = (486 + 136, 680 + 255);
(M1 => F) = (478, 723);
endspecify
endspecify
endmodule
(* abc9_lut=8 *)
@ -79,7 +79,7 @@ module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);
(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);
(M1 => F) = (478 + 136, 723 + 255);
(M2 => F) = (478, 723);
endspecify
endspecify
endmodule
(* abc9_lut=16 *)
@ -93,7 +93,7 @@ module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);
(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);
(M2 => F) = (478 + 136, 723 + 255);
(M3 => F) = (478, 723);
endspecify
endspecify
endmodule
module MUX2 (O, I0, I1, S0);
@ -212,7 +212,7 @@ module DFFS (output reg Q, input D, CLK, SET);
if (SET)
Q <= 1'b1;
else
Q <= D;
Q <= D;
end
endmodule // DFFS (positive clock edge; synchronous set)
@ -388,7 +388,7 @@ endmodule // DFFNE (negative clock edge; clock enable)
module DFFNS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
@ -399,7 +399,7 @@ module DFFNS (output reg Q, input D, CLK, SET);
if (SET)
Q <= 1'b1;
else
Q <= D;
Q <= D;
end
endmodule // DFFNS (negative clock edge; synchronous set)
@ -485,7 +485,7 @@ endmodule // DFFNP (negative clock edge; asynchronous preset)
module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
(PRESET => Q) = (1800, 2679);
@ -793,7 +793,7 @@ module OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);
parameter LSREN = "true";
endmodule
module OSER16(D15, D14, D13, D12, D11, D10,
module OSER16(D15, D14, D13, D12, D11, D10,
D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,
RESET, Q);
output Q;
@ -918,7 +918,7 @@ RESET, CALIB, D);
parameter LSREN = "true";
endmodule
module IDES16(Q15, Q14, Q13, Q12, Q11, Q10,
module IDES16(Q15, Q14, Q13, Q12, Q11, Q10,
Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
RESET, CALIB, D);
input D;

228
techlibs/gowin/cells_xtra_gw1n.v
View file

@ -36,7 +36,7 @@ endmodule
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
input SETN;
@ -47,9 +47,9 @@ endmodule
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
input D, CLK, RESET, MCLK;
output LAG, LEAD;
endmodule
@ -63,10 +63,10 @@ endmodule
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -132,9 +132,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [31:0] DO;
@ -142,11 +142,11 @@ endmodule
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -211,9 +211,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [35:0] DO;
@ -221,9 +221,9 @@ endmodule
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -289,18 +289,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [31:0] DO;
endmodule
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -365,20 +365,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [35:0] DO;
endmodule
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -444,8 +444,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSELA, BLKSELB;
@ -454,13 +454,13 @@ endmodule
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -525,8 +525,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [35:0] DI;
@ -535,15 +535,15 @@ endmodule
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -609,9 +609,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [15:0] DIA, DIB;
@ -620,16 +620,16 @@ endmodule
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -694,9 +694,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [17:0] DIA, DIB;
input [2:0] BLKSELA, BLKSELB;
@ -712,11 +712,11 @@ input CE,CLK,RESET;
input [17:0] SI,SBI;
output [17:0] SO,SBO;
output [17:0] DOUT;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -728,11 +728,11 @@ input CE,CLK,RESET;
input [8:0] SI,SBI;
output [8:0] SO,SBO;
output [8:0] DOUT;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -752,8 +752,8 @@ parameter OUT_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
@ -773,7 +773,7 @@ parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
@ -791,7 +791,7 @@ parameter OUT1_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
@ -814,9 +814,9 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
@ -836,7 +836,7 @@ input ACCLOAD;
output [53:0] DOUT;
output [54:0] CASO;
output [17:0] SOA, SOB;
parameter A0REG = 1'b0;
parameter A0REG = 1'b0;
parameter A1REG = 1'b0;
parameter B0REG = 1'b0;
parameter B1REG = 1'b0;
@ -851,7 +851,7 @@ parameter ACCLOAD_REG1 = 1'b0;
parameter BSIGN0_REG = 1'b0;
parameter BSIGN1_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
@ -875,12 +875,12 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
parameter PIPE_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
@ -891,13 +891,13 @@ input [54:0] CASI;
input CLK, CE, RESET;
output [53:0] DOUT;
output [54:0] CASO;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
@ -918,41 +918,41 @@ endmodule
module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3);
input CLKIN;
input CLKFB;
input RESET;
input RESET_P;
input RESET;
input RESET_P;
input RESET_I;
input RESET_S;
input [5:0] FBDSEL;
input [5:0] FBDSEL;
input [5:0] IDSEL;
input [5:0] ODSEL;
input [3:0] PSDA,FDLY;
input [3:0] PSDA,FDLY;
input [3:0] DUTYDA;
output CLKOUT;
output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0";
parameter FCLKIN = "100.0";
parameter DYN_IDIV_SEL= "false";
parameter IDIV_SEL = 0;
parameter IDIV_SEL = 0;
parameter DYN_FBDIV_SEL= "false";
parameter FBDIV_SEL = 0;
parameter FBDIV_SEL = 0;
parameter DYN_ODIV_SEL= "false";
parameter ODIV_SEL = 8;
parameter ODIV_SEL = 8;
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false";
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW1N-4";
endmodule
@ -1034,8 +1034,8 @@ input HCLKIN;
input RESETN;
input CALIB;
output CLKOUT;
parameter DIV_MODE = "2";
parameter GSREN = "false";
parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN(CLKIN, CE, CLKOUT);
@ -1049,9 +1049,9 @@ input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
output CLKOUT;
output FLAG;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT);
@ -1084,7 +1084,7 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule
module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
@ -1113,7 +1113,7 @@ module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
parameter DCS_MODE = "RISING";
endmodule
module DQCE(CLKIN, CE, CLKOUT);
@ -1123,7 +1123,7 @@ output CLKOUT;
endmodule
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule
@ -1153,7 +1153,7 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule
module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
@ -1175,5 +1175,5 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule

266
techlibs/gowin/cells_xtra_gw2a.v
View file

@ -36,8 +36,8 @@ endmodule
module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -47,10 +47,10 @@ endmodule
module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1;
input TX, PCLK, TCLK, RESET;
output Q0, Q1;
@ -58,8 +58,8 @@ endmodule
module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -69,8 +69,8 @@ endmodule
module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -80,11 +80,11 @@ endmodule
module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1, D2, D3;
input TX0, TX1;
input PCLK, FCLK, TCLK, RESET;
@ -93,11 +93,11 @@ endmodule
module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1, D2, D3, D4, D5, D6, D7;
input TX0, TX1, TX2, TX3;
input PCLK, FCLK, TCLK, RESET;
@ -106,7 +106,7 @@ endmodule
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
input SETN;
@ -117,9 +117,9 @@ endmodule
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
input D, CLK, RESET, MCLK;
output LAG, LEAD;
endmodule
@ -133,10 +133,10 @@ endmodule
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -202,9 +202,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [31:0] DO;
@ -212,11 +212,11 @@ endmodule
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -281,9 +281,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [35:0] DO;
@ -291,9 +291,9 @@ endmodule
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -359,18 +359,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [31:0] DO;
endmodule
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -435,20 +435,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [35:0] DO;
endmodule
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -514,8 +514,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSELA, BLKSELB;
@ -524,13 +524,13 @@ endmodule
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -595,8 +595,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [35:0] DI;
@ -605,15 +605,15 @@ endmodule
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -679,9 +679,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [15:0] DIA, DIB;
@ -690,16 +690,16 @@ endmodule
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -764,9 +764,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [17:0] DIA, DIB;
input [2:0] BLKSELA, BLKSELB;
@ -782,11 +782,11 @@ input CE,CLK,RESET;
input [17:0] SI,SBI;
output [17:0] SO,SBO;
output [17:0] DOUT;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -798,11 +798,11 @@ input CE,CLK,RESET;
input [8:0] SI,SBI;
output [8:0] SO,SBO;
output [8:0] DOUT;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -822,8 +822,8 @@ parameter OUT_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
@ -843,7 +843,7 @@ parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
@ -861,7 +861,7 @@ parameter OUT1_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
@ -884,9 +884,9 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
@ -906,7 +906,7 @@ input ACCLOAD;
output [53:0] DOUT;
output [54:0] CASO;
output [17:0] SOA, SOB;
parameter A0REG = 1'b0;
parameter A0REG = 1'b0;
parameter A1REG = 1'b0;
parameter B0REG = 1'b0;
parameter B1REG = 1'b0;
@ -921,7 +921,7 @@ parameter ACCLOAD_REG1 = 1'b0;
parameter BSIGN0_REG = 1'b0;
parameter BSIGN1_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
@ -945,12 +945,12 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
parameter PIPE_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
@ -961,13 +961,13 @@ input [54:0] CASI;
input CLK, CE, RESET;
output [53:0] DOUT;
output [54:0] CASO;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
@ -1002,27 +1002,27 @@ output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0";
parameter FCLKIN = "100.0";
parameter DYN_IDIV_SEL= "false";
parameter IDIV_SEL = 0;
parameter IDIV_SEL = 0;
parameter DYN_FBDIV_SEL= "false";
parameter FBDIV_SEL = 0;
parameter FBDIV_SEL = 0;
parameter DYN_ODIV_SEL= "false";
parameter ODIV_SEL = 8;
parameter ODIV_SEL = 8;
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false";
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW2A-18";
endmodule
@ -1063,8 +1063,8 @@ input HCLKIN;
input RESETN;
input CALIB;
output CLKOUT;
parameter DIV_MODE = "2";
parameter GSREN = "false";
parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN(CLKIN, CE, CLKOUT);
@ -1080,14 +1080,14 @@ input [2:0] RCLKSEL;
input [7:0] DLLSTEP;
input [7:0] WSTEP;
input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
output DQSR90, DQSW0, DQSW270;
output DQSR90, DQSW0, DQSW270;
output [2:0] RPOINT, WPOINT;
output RVALID,RBURST, RFLAG, WFLAG;
parameter FIFO_MODE_SEL = 1'b0;
parameter RD_PNTR = 3'b000;
parameter DQS_MODE = "X1";
parameter HWL = "false";
parameter GSREN = "false";
parameter FIFO_MODE_SEL = 1'b0;
parameter RD_PNTR = 3'b000;
parameter DQS_MODE = "X1";
parameter HWL = "false";
parameter GSREN = "false";
endmodule
module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG);
@ -1096,16 +1096,16 @@ input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
output CLKOUT;
output FLAG;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
parameter DCS_MODE = "RISING";
endmodule
module DQCE(CLKIN, CE, CLKOUT);
@ -1115,7 +1115,7 @@ output CLKOUT;
endmodule
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule

1836
techlibs/gowin/cells_xtra_gw5a.v
View file

File diff suppressed because it is too large Load diff