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https://github.com/YosysHQ/yosys
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Remove trailing whitespaces
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48a3dcc02a
commit
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317 changed files with 3136 additions and 3136 deletions
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@ -1,5 +1,5 @@
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module EFX_LUT4(
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output O,
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output O,
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input I0,
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input I1,
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input I2,
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@ -10,7 +10,7 @@ module EFX_LUT4(
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wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
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wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
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assign O = I0 ? s1[1] : s1[0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module EFX_ADD(
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@ -64,9 +64,9 @@ module EFX_FF(
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initial Q = 1'b0;
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generate
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if (SR_SYNC == 1)
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if (SR_SYNC == 1)
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begin
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if (SR_SYNC_PRIORITY == 1)
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if (SR_SYNC_PRIORITY == 1)
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begin
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always @(posedge clk)
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if (sr)
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@ -93,7 +93,7 @@ module EFX_FF(
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Q <= SR_VALUE;
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else if (ce)
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Q <= d;
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end
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endgenerate
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endmodule
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@ -108,16 +108,16 @@ module EFX_GBUFCE(
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wire ce;
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assign ce = CE_POLARITY ? CE : ~CE;
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assign O = I & ce;
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endmodule
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module EFX_RAM_5K
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# (
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parameter READ_WIDTH = 20,
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parameter WRITE_WIDTH = 20,
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localparam READ_ADDR_WIDTH =
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localparam READ_ADDR_WIDTH =
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(READ_WIDTH == 16) ? 8 : // 256x16
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(READ_WIDTH == 8) ? 9 : // 512x8
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(READ_WIDTH == 4) ? 10 : // 1024x4
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@ -126,8 +126,8 @@ module EFX_RAM_5K
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(READ_WIDTH == 20) ? 8 : // 256x20
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(READ_WIDTH == 10) ? 9 : // 512x10
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(READ_WIDTH == 5) ? 10 : -1, // 1024x5
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localparam WRITE_ADDR_WIDTH =
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localparam WRITE_ADDR_WIDTH =
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(WRITE_WIDTH == 16) ? 8 : // 256x16
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(WRITE_WIDTH == 8) ? 9 : // 512x8
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(WRITE_WIDTH == 4) ? 10 : // 1024x4
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@ -140,13 +140,13 @@ module EFX_RAM_5K
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(
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input [WRITE_WIDTH-1:0] WDATA,
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input [WRITE_ADDR_WIDTH-1:0] WADDR,
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input WE,
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input WE,
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(* clkbuf_sink *)
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input WCLK,
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input WCLKE,
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output [READ_WIDTH-1:0] RDATA,
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input WCLKE,
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output [READ_WIDTH-1:0] RDATA,
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input [READ_ADDR_WIDTH-1:0] RADDR,
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input RE,
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input RE,
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(* clkbuf_sink *)
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input RCLK
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);
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