mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-01 13:08:54 +00:00
Code Activity

Remove trailing whitespaces

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/efinix/arith_map.v
View file

@ -36,7 +36,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
@ -73,14 +73,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
.O(Y[i]),
.CO(COx[i])
);
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cout (
.I0(1'b0),
.I1(1'b0),
.CI(COx[i]),
.O(CO[i])
);
end: slice
end: slice
endgenerate
/* End implementation */

4
techlibs/efinix/brams_map.v
View file

@ -33,14 +33,14 @@ module $__EFINIX_5K_ (...);
PORT_W_WIDTH == 10 ? 9 :
8;
localparam READ_WIDTH =
localparam READ_WIDTH =
PORT_R_WIDTH == 1 ? 1 :
PORT_R_WIDTH == 2 ? 2 :
PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
(IS_5BIT ? 20 : 16);
localparam WRITE_WIDTH =
localparam WRITE_WIDTH =
PORT_W_WIDTH == 1 ? 1 :
PORT_W_WIDTH == 2 ? 2 :
PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :

28
techlibs/efinix/cells_sim.v
View file

@ -1,5 +1,5 @@
module EFX_LUT4(
output O,
output O,
input I0,
input I1,
input I2,
@ -10,7 +10,7 @@ module EFX_LUT4(
wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module EFX_ADD(
@ -64,9 +64,9 @@ module EFX_FF(
initial Q = 1'b0;
generate
if (SR_SYNC == 1)
if (SR_SYNC == 1)
begin
if (SR_SYNC_PRIORITY == 1)
if (SR_SYNC_PRIORITY == 1)
begin
always @(posedge clk)
if (sr)
@ -93,7 +93,7 @@ module EFX_FF(
Q <= SR_VALUE;
else if (ce)
Q <= d;
end
endgenerate
endmodule
@ -108,16 +108,16 @@ module EFX_GBUFCE(
wire ce;
assign ce = CE_POLARITY ? CE : ~CE;
assign O = I & ce;
endmodule
module EFX_RAM_5K
# (
parameter READ_WIDTH = 20,
parameter WRITE_WIDTH = 20,
localparam READ_ADDR_WIDTH =
localparam READ_ADDR_WIDTH =
(READ_WIDTH == 16) ? 8 : // 256x16
(READ_WIDTH == 8) ? 9 : // 512x8
(READ_WIDTH == 4) ? 10 : // 1024x4
@ -126,8 +126,8 @@ module EFX_RAM_5K
(READ_WIDTH == 20) ? 8 : // 256x20
(READ_WIDTH == 10) ? 9 : // 512x10
(READ_WIDTH == 5) ? 10 : -1, // 1024x5
localparam WRITE_ADDR_WIDTH =
localparam WRITE_ADDR_WIDTH =
(WRITE_WIDTH == 16) ? 8 : // 256x16
(WRITE_WIDTH == 8) ? 9 : // 512x8
(WRITE_WIDTH == 4) ? 10 : // 1024x4
@ -140,13 +140,13 @@ module EFX_RAM_5K
(
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
input WE,
(* clkbuf_sink *)
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
input RE,
(* clkbuf_sink *)
input RCLK
);

14
techlibs/efinix/efinix_fixcarry.cc
View file

@ -45,12 +45,12 @@ static void fix_carry_chain(Module *module)
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit bit_o = sigmap(cell->getPort(ID::O));
ci_bits.insert(bit_ci);
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
}
}
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
@ -60,8 +60,8 @@ static void fix_carry_chain(Module *module)
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
adders_to_fix_cells.push_back(cell);
@ -83,7 +83,7 @@ static void fix_carry_chain(Module *module)
c->setPort(ID(I1), State::S1);
c->setPort(ID::CI, State::S0);
c->setPort(ID::CO, new_bit);
cell->setPort(ID::CI, new_bit);
}
}
@ -102,7 +102,7 @@ struct EfinixCarryFixPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -115,7 +115,7 @@ struct EfinixCarryFixPass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found.\n");
fix_carry_chain(module);
fix_carry_chain(module);
}
} EfinixCarryFixPass;