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https://github.com/YosysHQ/yosys
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Remove trailing whitespaces
This commit is contained in:
Miodrag Milanovic
parent
48a3dcc02a
commit
a689342207
317 changed files with 3136 additions and 3136 deletions
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@ -116,7 +116,7 @@ struct CutpointPass : public Pass {
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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wire_drivers.insert(bit);
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for (auto wire : module->wires())
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if (wire->port_input)
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for (auto bit : sigmap(wire))
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@ -132,7 +132,7 @@ struct QbfSolutionType {
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//More importantly, we want to have the ability to port hole assignments to other modules with compatible
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//hole names and widths. Obviously in those cases source locations of the $anyconst cells will not match.
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//
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//Option 2 has the benefits previously described, but wire names can be changed automatically by
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//Option 2 has the benefits previously described, but wire names can be changed automatically by
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//optimization or techmapping passes, especially when (ex/im)porting from BLIF for optimization with ABC.
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//
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//The approach taken here is to allow both options. We write the assignment information for each bit of
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@ -155,7 +155,7 @@ void zinit(Const &v)
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struct SimInstance
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{
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SimShared *shared;
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std::string scope;
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Module *module;
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Cell *instance;
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@ -183,7 +183,7 @@ struct SimInstance
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State past_clk;
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State past_ce;
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State past_srst;
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FfData data;
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};
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@ -1050,7 +1050,7 @@ struct SimInstance
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}
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}
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}
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for (auto signal : signal_database)
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{
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if (shared->hdlname && signal.first->name.isPublic() && signal.first->has_attribute(ID::hdlname)) {
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@ -1182,7 +1182,7 @@ struct SimInstance
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{
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if (cell->is_mem_cell()) {
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std::string memid = cell->parameters.at(ID::MEMID).decode_string();
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for (auto &data : fst_memories[memid])
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for (auto &data : fst_memories[memid])
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{
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std::string v = shared->fst->valueOf(data.second);
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set_memory_state(memid, Const(data.first), Const::from_string(v));
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@ -1399,7 +1399,7 @@ struct SimWorker : SimShared
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}
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for(auto& writer : outputfiles)
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writer->write(use_signal);
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if (writeback) {
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pool<Module*> wbmods;
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top->writeback(wbmods);
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@ -1592,7 +1592,7 @@ struct SimWorker : SimShared
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if (start_time.time < fst->getStartTime())
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log_warning("Start time is before simulation file start time\n");
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startCount = fst->getStartTime();
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} else if (start_time.end)
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} else if (start_time.end)
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startCount = fst->getEndTime();
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else {
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startCount = start_time.time * pow10(start_time.scale - fst->getScale());
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@ -1605,7 +1605,7 @@ struct SimWorker : SimShared
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if (stop_time.time < fst->getStartTime())
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log_warning("Stop time is before simulation file start time\n");
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stopCount = fst->getStartTime();
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} else if (stop_time.end)
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} else if (stop_time.end)
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stopCount = fst->getEndTime();
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else {
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stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale());
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@ -1621,7 +1621,7 @@ struct SimWorker : SimShared
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bool initial = true;
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int cycle = 0;
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log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
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if (cycles_set)
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if (cycles_set)
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log(" for %d clock cycle(s)",numcycles);
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log("\n");
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bool all_samples = fst_clock.empty();
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@ -1839,9 +1839,9 @@ struct SimWorker : SimShared
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std::getline(f, line);
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if (line.size()==0) continue;
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if (line[0]=='#' || line[0]=='@' || line[0]=='.') {
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if (line[0]=='#' || line[0]=='@' || line[0]=='.') {
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if (line[0]!='.')
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curr_cycle = atoi(line.c_str()+1);
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curr_cycle = atoi(line.c_str()+1);
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else
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curr_cycle = -1; // force detect change
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@ -1907,7 +1907,7 @@ struct SimWorker : SimShared
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log_error("Cell %s not present in module %s\n",escaped_s.unescape(),topmod);
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if (!c->is_mem_cell())
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log_error("Cell %s is not memory cell in module %s\n",escaped_s.unescape(),topmod);
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Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2));
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Const data = Const::from_string(parts[2]);
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top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data);
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@ -2252,7 +2252,7 @@ struct SimWorker : SimShared
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if (start_time.time < fst->getStartTime())
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log_warning("Start time is before simulation file start time\n");
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startCount = fst->getStartTime();
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} else if (start_time.end)
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} else if (start_time.end)
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startCount = fst->getEndTime();
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else {
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startCount = start_time.time * pow10(start_time.scale - fst->getScale());
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@ -2265,7 +2265,7 @@ struct SimWorker : SimShared
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if (stop_time.time < fst->getStartTime())
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log_warning("Stop time is before simulation file start time\n");
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stopCount = fst->getStartTime();
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} else if (stop_time.end)
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} else if (stop_time.end)
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stopCount = fst->getEndTime();
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else {
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stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale());
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@ -2280,7 +2280,7 @@ struct SimWorker : SimShared
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int cycle = 0;
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log("Generate testbench data from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
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if (cycles_set)
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if (cycles_set)
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log(" for %d clock cycle(s)",numcycles);
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log("\n");
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@ -2351,22 +2351,22 @@ struct SimWorker : SimShared
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f << initstate.str();
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f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename);
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f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1);
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f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
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f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1);
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f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
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f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1);
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f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle);
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f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1);
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f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
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f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1);
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f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1);
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f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1);
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f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1);
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f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n";
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f << "\t\t\tend\n";
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f << "\t\tend\n";
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f << "\t\t$finish;\n";
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f << "\tend\n";
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f << "endmodule\n";
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@ -2483,7 +2483,7 @@ struct FSTWriter : public OutputWriter
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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worker->top->write_output_header(
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[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); },
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[this]() { fstWriterSetUpscope(fstfile); },
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@ -2632,7 +2632,7 @@ struct AIWWriter : public OutputWriter
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aiwfile << '0';
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}
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aiwfile << '\n';
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}
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}
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}
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std::ofstream aiwfile;
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@ -3038,7 +3038,7 @@ struct Fst2TbPass : public Pass {
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log("\n");
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log(" -n <integer>\n");
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log(" number of clock cycles to simulate (default: 20)\n");
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log("\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -159,7 +159,7 @@ void SynthPropWorker::run()
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if (tracing_data[module].names.size() == 0) return;
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if (!reset_name.empty()) {
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int width = tracing_data[module].names.size();
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int width = tracing_data[module].names.size();
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SigSpec reset = module->wire(reset_name);
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reset.extend_u0(width, true);
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