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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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2
passes/opt/muxpack.cc
View file

@ -159,7 +159,7 @@ struct MuxpackWorker
if (cell->type == ID($mux))
b_sig = sigmap(cell->getPort(ID::B));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig)
sigbit_with_non_chain_users.insert(a_bit);

32
passes/opt/opt_balance_tree.cc
View file

@ -73,15 +73,15 @@ struct OptBalanceTreeWorker {
// Base case: if we have only one source, return it
if (sources.size() == 1)
return sources[0];
// Base case: if we have two sources, create a single cell
if (sources.size() == 2) {
// Create a new cell of the same type
Cell* new_cell = module->addCell(NEW_ID, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
// Create output wire
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
if (cell_type == ID($add))
@ -89,7 +89,7 @@ struct OptBalanceTreeWorker {
else if (cell_type == ID($mul))
out_width = sources[0].size() + sources[1].size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, sources[0]);
new_cell->setPort(ID::B, sources[1]);
@ -97,26 +97,26 @@ struct OptBalanceTreeWorker {
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
// Update count and return output wire
cell_count[cell_type]++;
return out_wire;
}
// Recursive case: split sources into two groups and create subtrees
int mid = (sources.size() + 1) / 2;
vector<SigSpec> left_sources(sources.begin(), sources.begin() + mid);
vector<SigSpec> right_sources(sources.begin() + mid, sources.end());
SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell);
SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell);
// Create a cell to combine the two subtrees
Cell* new_cell = module->addCell(NEW_ID, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
// Create output wire
int out_width = cell->getParam(ID::Y_WIDTH).as_int();
if (cell_type == ID($add))
@ -124,7 +124,7 @@ struct OptBalanceTreeWorker {
else if (cell_type == ID($mul))
out_width = left_tree.size() + right_tree.size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, left_tree);
new_cell->setPort(ID::B, right_tree);
@ -132,7 +132,7 @@ struct OptBalanceTreeWorker {
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
// Update count and return output wire
cell_count[cell_type]++;
return out_wire;
@ -280,7 +280,7 @@ struct OptBalanceTreeWorker {
{
// Create a tree
log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", head_cell, GetSize(sources), inner_cells);
// Build a vector of all source signals
vector<SigSpec> source_signals;
vector<bool> signed_flags;
@ -295,10 +295,10 @@ struct OptBalanceTreeWorker {
if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) {
continue;
}
// Create the balanced tree
SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell);
// Connect the tree output to the head cell's output
SigSpec head_output = sigmap(head_cell->getPort(ID::Y));
int connect_width = std::min(head_output.size(), tree_output.size());
@ -313,7 +313,7 @@ struct OptBalanceTreeWorker {
}
}
}
// Remove all consumed cells, which now have been replaced by trees
for (auto cell : consumed_cells)
module->remove(cell);

4
passes/opt/opt_hier.cc
View file

@ -75,7 +75,7 @@ struct ModuleIndex {
} else {
classes[pair.second[i]].append(pair.first[i]);
}
}
}
}
}
@ -217,7 +217,7 @@ struct UsageData {
for (auto port_name : module->ports) {
Wire *port = module->wire(port_name);
log_assert(port);
if (port->port_input && port->port_output) {
// ignore bidirectional: hard to come up with sound handling
continue;

2
passes/opt/opt_lut.cc
View file

@ -296,7 +296,7 @@ struct OptLutWorker
luts_dlogic_inputs.erase(lut);
module->remove(lut);
eliminated_count++;
if (limit > 0)
limit--;

2
passes/opt/opt_share.cc
View file

@ -445,7 +445,7 @@ struct OptSharePass : public Pass {
while (mux_port_offset + op_conn_width < mux_port_size &&
op_outsig_offset + op_conn_width < op_outsig_size &&
mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width])
op_conn_width++;
op_conn_width++;
log_assert(op_conn_width >= 1);

8
passes/opt/peepopt_muldiv_c.pmg
View file

@ -55,19 +55,19 @@ code
int c_const_int = c_const.as_int(c_const_signed);
int b_const_int_shifted = b_const_int << offset;
// Helper lambdas for two's complement math
// Helper lambdas for two's complement math
auto sign2sComplement = [](auto value, int numBits) {
if (value & (1 << (numBits - 1))) {
return -1;
return -1;
} else {
return 1;
return 1;
}
};
auto twosComplement = [](auto value, int numBits) {
if (value & (1 << (numBits - 1))) {
return (~value) + 1; // invert bits before adding 1
} else {
return value;
return value;
}
};

4
passes/opt/peepopt_shiftadd.pmg
View file

@ -104,8 +104,8 @@ code
std::string location = shift->get_src_attribute();
if(shiftadd_max_ratio>0 && offset<0 && -offset*shiftadd_max_ratio > old_a.size()) {
log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) "
"was ignored to avoid high resource usage, see help peepopt\n",
log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) "
"was ignored to avoid high resource usage, see help peepopt\n",
location.c_str(), log_signal(old_a), log_signal(var_signal), -offset);
reject;
}