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Remove trailing whitespaces

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:24:59 +02:00
parent 48a3dcc02a
commit a689342207
317 changed files with 3136 additions and 3136 deletions
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2
docs/source/code_examples/fifo/Makefile
View file

@ -2,7 +2,7 @@ include ../../../common.mk
DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean
DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse
MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells
DOTS := $(addsuffix .dot,$(DOT_NAMES))

4
docs/source/code_examples/fifo/fifo.v
View file

@ -1,5 +1,5 @@
// address generator/counter
module addr_gen
module addr_gen
#( parameter MAX_DATA=256,
localparam AWIDTH = $clog2(MAX_DATA)
) ( input en, clk, rst,
@ -21,7 +21,7 @@ module addr_gen
endmodule //addr_gen
// Define our top level fifo entity
module fifo
module fifo
#( parameter MAX_DATA=256,
localparam AWIDTH = $clog2(MAX_DATA)
) ( input wen, ren, clk, rst,

2
docs/source/code_examples/fifo/fifo.ys
View file

@ -2,7 +2,7 @@
# throw in some extra text to match what we expect if we were opening an
# interactive terminal
log $ yosys fifo.v
log
log
log -- Parsing `fifo.v' using frontend ` -vlog2k' --
read_verilog -defer fifo.v

4
docs/source/code_examples/macro_commands/synth_ice40.ys
View file

@ -54,7 +54,7 @@ map_gates:
ice40_wrapcarry
techmap
opt -fast
abc -dff -D 1
abc -dff -D 1
ice40_opt
map_ffs:
@ -88,4 +88,4 @@ check:
stat
check -noinit
blackbox =A:whitebox

2
docs/source/code_examples/opt/opt_expr.ys
View file

@ -3,7 +3,7 @@ read_verilog <<EOT
module uut(
input a,
output y, z
);
);
assign y = a == a;
assign z = a != a;
endmodule

2
docs/source/code_examples/opt/opt_muxtree.ys
View file

@ -3,7 +3,7 @@ read_verilog <<EOT
module uut(
input a, b, c, d,
output y
);
);
assign y = a ? (a ? b : c) : d;
endmodule

4
docs/source/code_examples/show/cmos.ys
View file

@ -2,7 +2,7 @@
read_verilog cmos.v
prep -top cmos_demo
techmap
abc -liberty ../intro/mycells.lib;;
abc -liberty ../intro/mycells.lib;;
show -format dot -prefix cmos_00
# reset
@ -13,5 +13,5 @@ read_verilog cmos.v
prep -top cmos_demo
techmap
splitnets -ports
abc -liberty ../intro/mycells.lib;;
abc -liberty ../intro/mycells.lib;;
show -lib ../intro/mycells.v -format dot -prefix cmos_01