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Remove trailing whitespaces

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Miodrag Milanovic 2026-06-23 07:24:59 +02:00
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docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
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@ -18,7 +18,7 @@ be used to convert Verilog designs with simple assertions to BTOR format.
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========
This document was originally published in November 2013:
This document was originally published in November 2013:
:download:`Converting Verilog to BTOR PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
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