Remove trailing whitespaces

docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst

@@ -279,9 +279,9 @@ This document was originally published in April 2015:
    in line 13 provides a mini synthesis-script to be used to process this cell.
 
    .. code-block:: c
-      :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled 
-               using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a 
-         -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` 
+      :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled
+               using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a
+         -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx``
          set and booted with a custom setup routine written in ARM assembler.
       :name: sieve
 

docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst

@@ -18,7 +18,7 @@ be used to convert Verilog designs with simple assertions to BTOR format.
 Download
 ========
 
-This document was originally published in November 2013: 
+This document was originally published in November 2013:
 :download:`Converting Verilog to BTOR PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
 
 ..

docs/source/appendix/primer.rst

@@ -601,7 +601,7 @@ Let's consider the following BNF (in Bison syntax):
 	:class: width-helper invert-helper
 	:name: fig:Basics_parsetree
 
-	Example parse tree for the Verilog expression 
+	Example parse tree for the Verilog expression
 	:verilog:`assign foo = bar + 42;`
 
 The parser converts the token list to the parse tree in :numref:`Fig. %s
@@ -630,7 +630,7 @@ three-address-code intermediate representation. :cite:p:`Dragonbook`
 	:class: width-helper invert-helper
 	:name: fig:Basics_ast
 
-	Example abstract syntax tree for the Verilog expression 
+	Example abstract syntax tree for the Verilog expression
 	:verilog:`assign foo = bar + 42;`
 
 

docs/source/appendix/rtlil_text.rst

@@ -136,11 +136,11 @@ wires, memories, cells, processes, and connections.
 
     <module>            ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
     <module-stmt>       ::= module <id> <eol>
-    <module-body>       ::= (<param-stmt> 
+    <module-body>       ::= (<param-stmt>
                          |   <conn-stmt>
-                         |   <wire> 
-                         |   <memory> 
-                         |   <cell> 
+                         |   <wire>
+                         |   <memory>
+                         |   <cell>
                          |   <process>)*
     <param-stmt>        ::= parameter <id> <constant>? <eol>
     <constant>          ::= <value> | <integer> | <string>
@@ -170,9 +170,9 @@ See :ref:`sec:rtlil_sigspec` for an overview of signal specifications.
 
 .. code:: BNF
 
-    <sigspec> ::= <constant> 
+    <sigspec> ::= <constant>
                |  <wire-id>
-               |  <sigspec> [ <integer> (:<integer>)? ] 
+               |  <sigspec> [ <integer> (:<integer>)? ]
                |  { <sigspec>* }
 
 When a ``<wire-id>`` is specified, the wire must have been previously declared.
@@ -202,12 +202,12 @@ See :ref:`sec:rtlil_cell_wire` for an overview of wires.
     <wire>          ::= <attr-stmt>* <wire-stmt>
     <wire-stmt>     ::= wire <wire-option>* <wire-id> <eol>
     <wire-id>       ::= <id>
-    <wire-option>   ::= width <integer> 
-                     |  offset <integer> 
-                     |  input <integer> 
-                     |  output <integer> 
-                     |  inout <integer> 
-                     |  upto 
+    <wire-option>   ::= width <integer>
+                     |  offset <integer>
+                     |  input <integer>
+                     |  output <integer>
+                     |  inout <integer>
+                     |  upto
                      |  signed
 
 Memories
@@ -223,8 +223,8 @@ See :ref:`sec:rtlil_memory` for an overview of memory cells, and
 
     <memory>        ::= <attr-stmt>* <memory-stmt>
     <memory-stmt>   ::= memory <memory-option>* <id> <eol>
-    <memory-option> ::= width <integer> 
-                     |  size <integer> 
+    <memory-option> ::= width <integer>
+                     |  size <integer>
                      |  offset <integer>
 
 Cells
@@ -299,9 +299,9 @@ be:
 .. code:: BNF
 
     <sync>          ::= <sync-stmt> <update-stmt>*
-    <sync-stmt>     ::= sync <sync-type> <sigspec> <eol> 
+    <sync-stmt>     ::= sync <sync-type> <sigspec> <eol>
                      |  sync global <eol>
-                     |  sync init <eol> 
+                     |  sync init <eol>
                      |  sync always <eol>
     <sync-type>     ::= low | high | posedge | negedge | edge
     <update-stmt>   ::= update <dest-sigspec> <src-sigspec> <eol>