mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Merge pull request #3984 from YosysHQ/module_hdlname

Browse source 
verific: save original module name
This commit is contained in:
Miodrag Milanović 2023-10-05 19:41:00 +02:00 • committed by GitHub
commit a54e6f2d1f
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verific/verific.cc
View file

@ -1275,6 +1275,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", RTLIL::id2cstr(module->name));
} }
import_attributes(module->attributes, nl, nl); import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
const char *param_name ; const char *param_name ;
const char *param_value ; const char *param_value ;
MapIter mi; MapIter mi;