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fixup! rtlil: enable single-bit vector wires

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Emil J. Tywoniak 2025-05-06 16:57:34 +02:00
parent ab112b9b6b
commit a4d23c0847
1 changed files with 1 additions and 0 deletions
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frontends/ast/ast.cc
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@ -223,6 +223,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
was_checked = false; was_checked = false;
range_valid = false; range_valid = false;
range_swapped = false; range_swapped = false;
is_sbvector = false;
is_custom_type = false; is_custom_type = false;
port_id = 0; port_id = 0;
range_left = -1; range_left = -1;