From a4d23c0847dc2c03d462b11c6de0a40e656e0aee Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 6 May 2025 16:57:34 +0200
Subject: [PATCH] fixup! rtlil: enable single-bit vector wires

---
 frontends/ast/ast.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 5f95de35f..49b256d02 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -223,6 +223,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
 	was_checked = false;
 	range_valid = false;
 	range_swapped = false;
+	is_sbvector = false;
 	is_custom_type = false;
 	port_id = 0;
 	range_left = -1;