Merge d6b9158fa3 into d0a41d4f58

tests/pyosys/test_idstring_lifetime.py

@@ -0,0 +1,28 @@
+
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+d = ys.Design()
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass("hierarchy -top spm", d)
+
+external_idstring_holder_0 = None
+external_idstring_holder_1 = None
+
+def get_top_module_idstring():
+	global external_idstring_holder_0, external_idstring_holder_1
+	d = ys.Design()
+	ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+	ys.run_pass("hierarchy -top spm", d)
+	external_idstring_holder_0 = d.top_module().name
+	for cell in d.top_module().cells_:
+		print(f"TARGETED: {cell}", flush=True)
+		external_idstring_holder_1 = cell
+		break
+	# d deallocates
+
+get_top_module_idstring()
+print(external_idstring_holder_0, flush=True)
+print(external_idstring_holder_1, flush=True)

tests/pyosys/test_indirect_inheritance.py

@@ -0,0 +1,15 @@
+
+from pyosys import libyosys as ys
+from pathlib import Path
+
+__file_dir__ = Path(__file__).absolute().parent
+
+
+d = ys.Design()
+ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
+ys.run_pass("hierarchy -top spm", d)
+
+for idstr, cell in d.top_module().cells_.items():
+    cell.set_bool_attribute("\\set")
+    print(cell.attributes)
+    break

tests/pyosys/test_monitor.py

@@ -14,7 +14,7 @@ class Monitor(ys.Monitor):
 		self.mods.append(mod.name.str())
 
 m = Monitor()
-d.monitors.add(m)
+d.monitors = [m]
 
 ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
 ys.run_pass("hierarchy -top spm", d)