mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
d6b9158fa3
- consistently use value semantics for objects passed along FFI boundary (not ideal but matches previous behavior) - add new overload of RTLIL::Module: addMemory that does not require a "donor" object - the idea is `Module`, `Memory`, `Wire`, `Cell` and `Process` cannot be directly constructed in Python and can only be added to the existing memory hierarchy in `Design` using the `add` methods - `Memory` requiring a donor object was the odd one out here - fix superclass member wrapping only looking at direct superclass for inheritance instead of recursively checking superclasses - fix superclass member wrapping not using superclass's denylists - fix Design's `__str__` function not returning a string - fix the generator crashing if there's any `std::function` in a header - misc: add a crude `__repr__` based on `__str__`
22 lines
445 B
Python
22 lines
445 B
Python
from pyosys import libyosys as ys
|
|
from pathlib import Path
|
|
|
|
__file_dir__ = Path(__file__).absolute().parent
|
|
|
|
d = ys.Design()
|
|
|
|
class Monitor(ys.Monitor):
|
|
def __init__(self):
|
|
super().__init__()
|
|
self.mods = []
|
|
|
|
def notify_module_add(self, mod):
|
|
self.mods.append(mod.name.str())
|
|
|
|
m = Monitor()
|
|
d.monitors = [m]
|
|
|
|
ys.run_pass(f"read_verilog {__file_dir__ / 'spm.cut.v.gz'}", d)
|
|
ys.run_pass("hierarchy -top spm", d)
|
|
|
|
assert m.mods == ["\\spm"]
|