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More work on example_synth

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Added highlighting in (most) schematics.
Written down to end of coarse-grain, with a couple of TODOs for filling in gaps.
Includes `techmap_synth.rst` stub.
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Krystine Sherwin 2023-12-18 17:49:15 +13:00
parent 742ec78ca3
commit a33b1b6059
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4 changed files with 196 additions and 45 deletions
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41
docs/source/code_examples/fifo/fifo.ys
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@ -9,31 +9,54 @@ read_verilog -defer fifo.v
# turn command echoes on to use the log output as a console session
echo on
hierarchy -top addr_gen
show -notitle -format dot -prefix addr_gen_hier
select -set new_cells t:*
show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_hier
# ========================================================
proc
show -notitle -format dot -prefix addr_gen_proc
select -set new_cells t:$mux t:*dff
show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc
# ========================================================
opt_clean
show -notitle -format dot -prefix addr_gen_clean
# ========================================================
design -reset
read_verilog fifo.v
hierarchy -check -top fifo
proc
show -notitle -format dot -prefix rdata_proc o:rdata %ci*
show -color maroon3 c:fifo_reader -notitle -format dot -prefix rdata_proc o:rdata %ci*
# ========================================================
flatten
flatten;;
show -notitle -format dot -prefix rdata_flat o:rdata %ci*
# ========================================================
opt_clean
show -notitle -format dot -prefix fifo_flat
opt_dff
select -set new_cells t:$adffe
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci*
# ========================================================
memory_dff
select -set new_cells t:$memrd_v2
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci*
# ========================================================
alumacc
select -set new_cells t:$alu t:$macc
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
# ========================================================
design -reset
read_verilog fifo.v
synth_ice40 -dsp -top fifo
show -notitle -format dot -prefix fifo_synth
stat
synth_ice40 -top fifo -run begin:map_ram
# memory_collect
# opt
select -set new_cells t:$mem_v2
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse o:rdata %ci*