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Merge remote-tracking branch 'origin/master' into xc7dsp

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Eddie Hung 2019-09-12 12:11:11 -07:00
commit a1123b095c
9 changed files with 110 additions and 13 deletions
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12
tests/various/equiv_opt_multiclock.ys Normal file
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read_verilog <<EOT
module top(input clk, pre, d, output reg q);
always @(posedge clk, posedge pre)
if (pre)
q <= 1'b1;
else
q <= d;
endmodule
EOT
prep
equiv_opt -assert -multiclock -map +/simcells.v synth