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Fix try_as_const/as_wire/as_chunk
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parent
000c081965
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a0e9e2d364
1 changed files with 12 additions and 9 deletions
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@ -5625,11 +5625,12 @@ std::optional<RTLIL::Const> RTLIL::SigSpec::try_as_const() const
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{
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{
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cover("kernel.rtlil.sigspec.as_const");
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cover("kernel.rtlil.sigspec.as_const");
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auto it = chunks().begin();
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Chunks cs = chunks();
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if (it == chunks().end())
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auto it = cs.begin();
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if (it == cs.end())
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return RTLIL::Const();
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return RTLIL::Const();
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SigChunk chunk = *it;
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SigChunk chunk = *it;
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if (chunk.wire != NULL || ++it != chunks().end())
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if (chunk.wire != NULL || ++it != cs.end())
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return std::nullopt;
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return std::nullopt;
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return RTLIL::Const(std::move(chunk.data));
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return RTLIL::Const(std::move(chunk.data));
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}
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}
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@ -5647,10 +5648,11 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const
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{
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{
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cover("kernel.rtlil.sigspec.as_wire");
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cover("kernel.rtlil.sigspec.as_wire");
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auto it = chunks().begin();
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Chunks cs = chunks();
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log_assert(it != chunks().end());
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auto it = cs.begin();
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log_assert(it != cs.end());
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RTLIL::SigChunk chunk = *it;
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RTLIL::SigChunk chunk = *it;
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log_assert(++it == chunks().end() && chunk.wire && chunk.wire->width == width_);
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log_assert(++it == cs.end() && chunk.wire && chunk.wire->width == width_);
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return chunk.wire;
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return chunk.wire;
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}
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}
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@ -5658,10 +5660,11 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
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{
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{
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cover("kernel.rtlil.sigspec.as_chunk");
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cover("kernel.rtlil.sigspec.as_chunk");
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auto it = chunks().begin();
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Chunks cs = chunks();
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log_assert(it != chunks().end());
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auto it = cs.begin();
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log_assert(it != cs.end());
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RTLIL::SigChunk chunk = *it;
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RTLIL::SigChunk chunk = *it;
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log_assert(++it == chunks().end());
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log_assert(++it == cs.end());
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return chunk;
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return chunk;
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}
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}
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