From 9f62dd6e0e114c223f5d7928ad6fb1e52a81659e Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Thu, 14 Aug 2025 16:12:53 +0200
Subject: [PATCH] WIP add placeholder $connect cell

---
 kernel/celltypes.h      |  1 +
 kernel/rtlil.cc         |  7 +++++++
 passes/opt/opt_clean.cc | 14 +++++++++++++-
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 11640c25f..81aa3f399 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -103,6 +103,7 @@ struct CellTypes
 		setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
 		setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
 		setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
+		setup_type(ID($connect), {ID::A, ID::Y}, {ID::A, ID::Y});
 		setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
 		setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
 		setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 0250346d1..7cd6326fa 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1475,6 +1475,13 @@ namespace {
 				return;
 			}
 
+			if (cell->type == ID($connect)) {
+				port(ID::A, param(ID::WIDTH));
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+
 			if (cell->type.in(ID($not), ID($pos), ID($neg))) {
 				param_bool(ID::A_SIGNED);
 				port(ID::A, param(ID::A_WIDTH));
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 620b38813..9e505a2ac 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -601,11 +601,23 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
 
 	std::vector<RTLIL::Cell*> delcells;
 	for (auto cell : module->cells())
-		if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
+		if (cell->type.in(ID($pos), ID($_BUF_), ID($buf), ID($connect)) && !cell->has_keep_attr()) {
 			bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
 			RTLIL::SigSpec a = cell->getPort(ID::A);
 			RTLIL::SigSpec y = cell->getPort(ID::Y);
 			a.extend_u0(GetSize(y), is_signed);
+			if (a.has_const(State::Sz)) {
+					RTLIL::SigSpec new_a;
+					RTLIL::SigSpec new_y;
+					for (int i = 0; i < GetSize(a); i++) {
+							if (a[i] == State::Sz)
+									continue;
+							new_a.append(a[i]);
+							new_y.append(y[i]);
+					}
+					a = std::move(new_a);
+					y = std::move(new_y);
+			}
 			module->connect(y, a);
 			delcells.push_back(cell);
 		}