mirror of
https://github.com/YosysHQ/yosys
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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
This commit is contained in:
Eddie Hung
commit
9f3cb981d7
9 changed files with 418 additions and 90 deletions
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@ -46,6 +46,7 @@ IdString RTLIL::ID::Y;
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IdString RTLIL::ID::keep;
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IdString RTLIL::ID::whitebox;
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IdString RTLIL::ID::blackbox;
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dict<std::string, std::string> RTLIL::constpad;
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RTLIL::Const::Const()
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{
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@ -377,6 +377,8 @@ namespace RTLIL
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extern IdString blackbox;
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};
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extern dict<std::string, std::string> constpad;
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static inline std::string escape_id(std::string str) {
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if (str.size() > 0 && str[0] != '\\' && str[0] != '$')
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return "\\" + str;
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@ -70,8 +70,10 @@ struct ScratchpadPass : public Pass {
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{
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if (args[argidx] == "-get" && argidx+1 < args.size()) {
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string identifier = args[++argidx];
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if (design->scratchpad.count(identifier)){
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if (design->scratchpad.count(identifier)) {
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log("%s\n", design->scratchpad_get_string(identifier).c_str());
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} else if (RTLIL::constpad.count(identifier)) {
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log("%s\n", RTLIL::constpad.at(identifier).c_str());
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} else {
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log("\"%s\" not set\n", identifier.c_str());
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}
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@ -79,6 +81,8 @@ struct ScratchpadPass : public Pass {
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}
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if (args[argidx] == "-set" && argidx+2 < args.size()) {
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string identifier = args[++argidx];
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if (RTLIL::constpad.count(identifier))
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log_error("scratchpad entry \"%s\" is a global constant\n", identifier.c_str());
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string value = args[++argidx];
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if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2);
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design->scratchpad_set_string(identifier, value);
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@ -92,8 +96,15 @@ struct ScratchpadPass : public Pass {
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if (args[argidx] == "-copy" && argidx+2 < args.size()) {
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string identifier_from = args[++argidx];
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string identifier_to = args[++argidx];
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if (design->scratchpad.count(identifier_from) == 0) log_error("\"%s\" not set\n", identifier_from.c_str());
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string value = design->scratchpad_get_string(identifier_from);
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string value;
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if (design->scratchpad.count(identifier_from))
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value = design->scratchpad_get_string(identifier_from);
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else if (RTLIL::constpad.count(identifier_from))
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value = RTLIL::constpad.at(identifier_from);
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else
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log_error("\"%s\" not set\n", identifier_from.c_str());
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if (RTLIL::constpad.count(identifier_to))
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log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to.c_str());
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design->scratchpad_set_string(identifier_to, value);
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continue;
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}
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@ -102,10 +113,10 @@ struct ScratchpadPass : public Pass {
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string expected = args[++argidx];
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if (expected.front() == '\"' && expected.back() == '\"') expected = expected.substr(1, expected.size() - 2);
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if (design->scratchpad.count(identifier) == 0)
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log_error("Assertion failed: scratchpad entry '%s' is not defined\n", identifier.c_str());
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log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
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string value = design->scratchpad_get_string(identifier);
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if (value != expected) {
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log_error("Assertion failed: scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n",
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log_error("scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n",
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identifier.c_str(), value.c_str(), expected.c_str());
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}
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continue;
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@ -113,13 +124,13 @@ struct ScratchpadPass : public Pass {
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if (args[argidx] == "-assert-set" && argidx+1 < args.size()) {
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string identifier = args[++argidx];
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if (design->scratchpad.count(identifier) == 0)
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log_error("Assertion failed: scratchpad entry '%s' is not defined\n", identifier.c_str());
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log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
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continue;
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}
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if (args[argidx] == "-assert-unset" && argidx+1 < args.size()) {
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string identifier = args[++argidx];
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if (design->scratchpad.count(identifier) > 0)
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log_error("Assertion failed: scratchpad entry '%s' is defined\n", identifier.c_str());
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log_error("scratchpad entry '%s' is defined\n", identifier.c_str());
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continue;
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}
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break;
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@ -18,18 +18,69 @@
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*
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*/
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// [[CITE]] ABC
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// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
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// http://www.eecs.berkeley.edu/~alanmi/abc/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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// abc9_exe.cc
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std::string fold_abc9_cmd(std::string str);
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Abc9Pass : public ScriptPass
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{
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Abc9Pass() : ScriptPass("abc9", "use ABC9 for technology mapping") { }
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void on_register() YS_OVERRIDE
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{
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RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
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RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
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RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R} -v";
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// Based on ABC's &flow
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RTLIL::constpad["abc9.script.flow"] = "+&scorr; &sweep;" \
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"&dch -C 500;" \
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/* Round 1 */ \
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/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &dsdb;" \
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/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &syn2 -m -R 10; &dsdb;" \
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"&blut -a -K 6;" \
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/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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/* Round 2 */ \
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"&st; &sopb;" \
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/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &dsdb;" \
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/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &syn2 -m -R 10; &dsdb;" \
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"&blut -a -K 6;" \
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/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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/* Round 3 */ \
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/* Map 1 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &dsdb;" \
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/* Map 2 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;" \
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"&st; &syn2 -m -R 10; &dsdb;" \
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"&blut -a -K 6;" \
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/* Map 3 */ "&unmap; &if {C} {W} {D} {R} -v; &save; &load; &mfs;";
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// Based on ABC's &flow2
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RTLIL::constpad["abc9.script.flow2"] = "+&scorr; &sweep;" \
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/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
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/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
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"&load; &st; &sopb -R 10 -C 4; " \
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/* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
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/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
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"&load";
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// Based on ABC's &flow3
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RTLIL::constpad["abc9.script.flow3"] = "+&scorr; &sweep;" \
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"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
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"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
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"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
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"&mfs";
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}
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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@ -57,14 +108,12 @@ struct Abc9Pass : public ScriptPass
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log(" replaced with blanks before the string is passed to ABC.\n");
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log("\n");
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log(" if no -script parameter is given, the following scripts are used:\n");
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//FIXME:
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//log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
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log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
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log("\n");
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log(" -fast\n");
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log(" use different default scripts that are slightly faster (at the cost\n");
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log(" of output quality):\n");
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//FIXME:
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//log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
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log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
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log("\n");
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log(" -D <picoseconds>\n");
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log(" set delay target. the string {D} in the default scripts above is\n");
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@ -104,7 +153,7 @@ struct Abc9Pass : public ScriptPass
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log(" command output is identical across runs.\n");
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log("\n");
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log(" -box <file>\n");
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log(" pass this file with box library to ABC. Use with -lut.\n");
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log(" pass this file with box library to ABC.\n");
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log("\n");
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log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
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log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
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@ -139,6 +188,11 @@ struct Abc9Pass : public ScriptPass
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dff_mode = design->scratchpad_get_bool("abc9.dff", dff_mode);
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cleanup = !design->scratchpad_get_bool("abc9.nocleanup", !cleanup);
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if (design->scratchpad_get_bool("abc9.debug")) {
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cleanup = false;
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exe_cmd << " -showtmp";
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}
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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@ -150,13 +204,13 @@ struct Abc9Pass : public ScriptPass
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continue;
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}
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if (arg == "-fast" || /* arg == "-dff" || */
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/* arg == "-nocleanup" || */ arg == "-showtmp" ||
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arg == "-nomfs") {
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/* arg == "-nocleanup" || */ arg == "-showtmp") {
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exe_cmd << " " << arg;
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continue;
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}
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if (arg == "-dff") {
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dff_mode = true;
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exe_cmd << " " << arg;
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continue;
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}
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if (arg == "-nocleanup") {
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@ -22,20 +22,6 @@
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// Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
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// http://www.eecs.berkeley.edu/~alanmi/abc/
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#if 0
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// Based on &flow3 - better QoR but more experimental
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#define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
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"&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
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"&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
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"&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
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"&mfs; &ps -l"
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#else
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#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
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#endif
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#define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
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#include "kernel/register.h"
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#include "kernel/log.h"
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@ -48,6 +34,25 @@
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extern "C" int Abc_RealMain(int argc, char *argv[]);
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#endif
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std::string fold_abc9_cmd(std::string str)
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{
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std::string token, new_str = " ";
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int char_counter = 10;
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for (size_t i = 0; i <= str.size(); i++) {
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if (i < str.size())
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token += str[i];
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if (i == str.size() || str[i] == ';') {
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if (char_counter + token.size() > 75)
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new_str += "\n ", char_counter = 14;
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new_str += token, char_counter += token.size();
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token.clear();
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}
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}
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return new_str;
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}
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -73,25 +78,6 @@ std::string add_echos_to_abc9_cmd(std::string str)
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return new_str;
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}
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std::string fold_abc9_cmd(std::string str)
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{
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std::string token, new_str = " ";
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int char_counter = 10;
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for (size_t i = 0; i <= str.size(); i++) {
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if (i < str.size())
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token += str[i];
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if (i == str.size() || str[i] == ';') {
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if (char_counter + token.size() > 75)
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new_str += "\n ", char_counter = 14;
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new_str += token, char_counter += token.size();
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token.clear();
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}
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}
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return new_str;
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}
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std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
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{
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if (show_tempdir)
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@ -177,9 +163,9 @@ struct abc9_output_filter
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};
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void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe_file,
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vector<int> lut_costs, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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vector<int> lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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bool show_tempdir, std::string box_file, std::string lut_file,
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std::string wire_delay, bool nomfs, std::string tempdir_name
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std::string wire_delay, std::string tempdir_name
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)
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{
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//FIXME:
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@ -188,20 +174,15 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
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std::string abc9_script;
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if (!lut_costs.empty()) {
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if (!lut_costs.empty())
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abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
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if (!box_file.empty())
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abc9_script += stringf("read_box %s; ", box_file.c_str());
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}
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else
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if (!lut_file.empty()) {
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else if (!lut_file.empty())
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abc9_script += stringf("read_lut %s; ", lut_file.c_str());
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if (!box_file.empty())
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abc9_script += stringf("read_box %s; ", box_file.c_str());
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}
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else
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log_abort();
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log_assert(!box_file.empty());
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abc9_script += stringf("read_box %s; ", box_file.c_str());
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abc9_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
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if (!script_file.empty()) {
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@ -216,7 +197,8 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
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} else
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abc9_script += stringf("source %s", script_file.c_str());
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} else if (!lut_costs.empty() || !lut_file.empty()) {
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abc9_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
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abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)
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: RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos);
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} else
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log_abort();
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@ -229,11 +211,26 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
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for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
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abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
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if (nomfs)
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for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
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abc9_script = abc9_script.erase(pos, strlen("&mfs"));
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std::string C;
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if (design->scratchpad.count("abc9.if.C"))
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C = "-C " + design->scratchpad_get_string("abc9.if.C");
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for (size_t pos = abc9_script.find("{C}"); pos != std::string::npos; pos = abc9_script.find("{C}", pos))
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abc9_script = abc9_script.substr(0, pos) + C + abc9_script.substr(pos+3);
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abc9_script += stringf("; &write -n %s/output.aig", tempdir_name.c_str());
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std::string R;
|
||||
if (design->scratchpad.count("abc9.if.R"))
|
||||
R = "-R " + design->scratchpad_get_string("abc9.if.R");
|
||||
for (size_t pos = abc9_script.find("{R}"); pos != std::string::npos; pos = abc9_script.find("{R}", pos))
|
||||
abc9_script = abc9_script.substr(0, pos) + R + abc9_script.substr(pos+3);
|
||||
|
||||
abc9_script += stringf("; &ps -l; &write -n %s/output.aig;", tempdir_name.c_str());
|
||||
if (design->scratchpad_get_bool("abc9.verify")) {
|
||||
if (dff_mode)
|
||||
abc9_script += "verify -s;";
|
||||
else
|
||||
abc9_script += "verify;";
|
||||
}
|
||||
abc9_script += "time";
|
||||
abc9_script = add_echos_to_abc9_cmd(abc9_script);
|
||||
|
||||
for (size_t i = 0; i+1 < abc9_script.size(); i++)
|
||||
|
|
@ -313,12 +310,12 @@ struct Abc9ExePass : public Pass {
|
|||
log(" replaced with blanks before the string is passed to ABC.\n");
|
||||
log("\n");
|
||||
log(" if no -script parameter is given, the following scripts are used:\n");
|
||||
log("%s\n", fold_abc9_cmd(ABC_COMMAND_LUT).c_str());
|
||||
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
|
||||
log("\n");
|
||||
log(" -fast\n");
|
||||
log(" use different default scripts that are slightly faster (at the cost\n");
|
||||
log(" of output quality):\n");
|
||||
log("%s\n", fold_abc9_cmd(ABC_FAST_COMMAND_LUT).c_str());
|
||||
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
|
||||
log("\n");
|
||||
log(" -D <picoseconds>\n");
|
||||
log(" set delay target. the string {D} in the default scripts above is\n");
|
||||
|
|
@ -350,7 +347,7 @@ struct Abc9ExePass : public Pass {
|
|||
log(" command output is identical across runs.\n");
|
||||
log("\n");
|
||||
log(" -box <file>\n");
|
||||
log(" pass this file with box library to ABC. Use with -lut.\n");
|
||||
log(" pass this file with box library to ABC.\n");
|
||||
log("\n");
|
||||
log(" -cwd <dir>\n");
|
||||
log(" use this as the current working directory, inside which the 'input.xaig'\n");
|
||||
|
|
@ -379,9 +376,8 @@ struct Abc9ExePass : public Pass {
|
|||
std::string script_file, clk_str, box_file, lut_file;
|
||||
std::string delay_target, lutin_shared = "-S 1", wire_delay;
|
||||
std::string tempdir_name;
|
||||
bool fast_mode = false;
|
||||
bool fast_mode = false, dff_mode = false;
|
||||
bool show_tempdir = false;
|
||||
bool nomfs = false;
|
||||
vector<int> lut_costs;
|
||||
|
||||
#if 0
|
||||
|
|
@ -405,12 +401,12 @@ struct Abc9ExePass : public Pass {
|
|||
lut_arg = design->scratchpad_get_string("abc9.lut", lut_arg);
|
||||
luts_arg = design->scratchpad_get_string("abc9.luts", luts_arg);
|
||||
fast_mode = design->scratchpad_get_bool("abc9.fast", fast_mode);
|
||||
dff_mode = design->scratchpad_get_bool("abc9.dff", dff_mode);
|
||||
show_tempdir = design->scratchpad_get_bool("abc9.showtmp", show_tempdir);
|
||||
box_file = design->scratchpad_get_string("abc9.box", box_file);
|
||||
if (design->scratchpad.count("abc9.W")) {
|
||||
wire_delay = "-W " + design->scratchpad_get_string("abc9.W");
|
||||
}
|
||||
nomfs = design->scratchpad_get_bool("abc9.nomfs", nomfs);
|
||||
|
||||
size_t argidx;
|
||||
char pwd [PATH_MAX];
|
||||
|
|
@ -448,6 +444,10 @@ struct Abc9ExePass : public Pass {
|
|||
fast_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-dff") {
|
||||
dff_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-showtmp") {
|
||||
show_tempdir = true;
|
||||
continue;
|
||||
|
|
@ -460,10 +460,6 @@ struct Abc9ExePass : public Pass {
|
|||
wire_delay = "-W " + args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (arg == "-nomfs") {
|
||||
nomfs = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-cwd" && argidx+1 < args.size()) {
|
||||
tempdir_name = args[++argidx];
|
||||
continue;
|
||||
|
|
@ -530,9 +526,9 @@ struct Abc9ExePass : public Pass {
|
|||
log_cmd_error("abc9_exe '-cwd' option is mandatory.\n");
|
||||
|
||||
|
||||
abc9_module(design, script_file, exe_file, lut_costs,
|
||||
abc9_module(design, script_file, exe_file, lut_costs, dff_mode,
|
||||
delay_target, lutin_shared, fast_mode, show_tempdir,
|
||||
box_file, lut_file, wire_delay, nomfs, tempdir_name);
|
||||
box_file, lut_file, wire_delay, tempdir_name);
|
||||
}
|
||||
} Abc9ExePass;
|
||||
|
||||
|
|
|
|||
|
|
@ -102,8 +102,8 @@ struct SynthIce40Pass : public ScriptPass
|
|||
log("\n");
|
||||
}
|
||||
|
||||
string top_opt, blif_file, edif_file, json_file, abc, device_opt;
|
||||
bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr;
|
||||
string top_opt, blif_file, edif_file, json_file, device_opt;
|
||||
bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9;
|
||||
int min_ce_use;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
|
|
@ -122,7 +122,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
noabc = false;
|
||||
abc2 = false;
|
||||
vpr = false;
|
||||
abc = "abc";
|
||||
abc9 = false;
|
||||
device_opt = "hx";
|
||||
}
|
||||
|
||||
|
|
@ -207,7 +207,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc = "abc9";
|
||||
abc9 = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-device" && argidx+1 < args.size()) {
|
||||
|
|
@ -223,7 +223,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
|
||||
log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
|
||||
|
||||
if (abc == "abc9" && retime)
|
||||
if (abc9 && retime)
|
||||
log_cmd_error("-retime option not currently compatible with -abc9!\n");
|
||||
|
||||
log_header(design, "Executing SYNTH_ICE40 pass.\n");
|
||||
|
|
@ -316,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
|
||||
}
|
||||
if (retime || help_mode)
|
||||
run(abc + " -dff -D 1", "(only if -retime)");
|
||||
run("abc -dff -D 1", "(only if -retime)");
|
||||
run("ice40_opt");
|
||||
}
|
||||
|
||||
|
|
@ -340,7 +340,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
if (check_label("map_luts"))
|
||||
{
|
||||
if (abc2 || help_mode) {
|
||||
run(abc, " (only if -abc2)");
|
||||
run("abc", " (only if -abc2)");
|
||||
run("ice40_opt", "(only if -abc2)");
|
||||
}
|
||||
run("techmap -map +/ice40/latches_map.v");
|
||||
|
|
@ -349,7 +349,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
|
||||
}
|
||||
if (!noabc) {
|
||||
if (abc == "abc9") {
|
||||
if (abc9) {
|
||||
run("read_verilog -icells -lib +/ice40/abc9_model.v");
|
||||
int wire_delay;
|
||||
if (device_opt == "lp")
|
||||
|
|
@ -358,10 +358,10 @@ struct SynthIce40Pass : public ScriptPass
|
|||
wire_delay = 750;
|
||||
else
|
||||
wire_delay = 250;
|
||||
run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
|
||||
run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
|
||||
}
|
||||
else
|
||||
run(abc + " -dress -lut 4", "(skip if -noabc)");
|
||||
run("abc -dress -lut 4", "(skip if -noabc)");
|
||||
}
|
||||
run("ice40_wrapcarry -unwrap");
|
||||
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
|
||||
|
|
|
|||
|
|
@ -26,13 +26,16 @@
|
|||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
#define XC7_WIRE_DELAY 300 // Number with which ABC will map a 6-input gate
|
||||
// to one LUT6 (instead of a LUT5 + LUT2)
|
||||
|
||||
struct SynthXilinxPass : public ScriptPass
|
||||
{
|
||||
SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
|
||||
|
||||
void on_register() YS_OVERRIDE
|
||||
{
|
||||
RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
|
||||
// to one LUT6 (instead of a LUT5 + LUT2)
|
||||
}
|
||||
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
|
|
@ -555,7 +558,11 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("techmap " + techmap_args);
|
||||
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
|
||||
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
|
||||
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
|
||||
auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
|
||||
if (active_design->scratchpad.count(k))
|
||||
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
|
||||
else
|
||||
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
|
||||
if (nowidelut)
|
||||
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
|
||||
else
|
||||
|
|
|
|||
217
tests/arch/ice40/bug1626.ys
Normal file
217
tests/arch/ice40/bug1626.ys
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
read_ilang <<EOT
|
||||
# Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os)
|
||||
autoidx 2815
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9"
|
||||
attribute \cells_not_processed 1
|
||||
attribute \dynports 1
|
||||
module \ahb_async_sram_halfwidth
|
||||
parameter \DEPTH
|
||||
parameter \W_ADDR
|
||||
parameter \W_BYTEADDR
|
||||
parameter \W_DATA
|
||||
parameter \W_SRAM_ADDR
|
||||
parameter \W_SRAM_DATA
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
|
||||
wire $0\addr_lsb[0:0]
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
|
||||
wire $0\hready_r[0:0]
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
|
||||
wire $0\long_dphase[0:0]
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
|
||||
wire width 16 $0\rdata_buf[15:0]
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
|
||||
wire $0\read_dph[0:0]
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
|
||||
wire $0\write_dph[0:0]
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
|
||||
wire width 32 $add$../hdl/mem/ahb_async_sram_halfwidth.v:63$2433_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
|
||||
wire width 16 $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
|
||||
wire $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2450_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2451_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2452_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2453_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2454_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2455_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2456_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2457_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2458_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2459_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:118$2444_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:133"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:133$2449_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2461_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2463_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:58$2425_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2426_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2427_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2429_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
|
||||
wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:104"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:104$2442_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:118$2443_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:125"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:125$2446_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:132$2447_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:59$2428_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:81"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:81$2438_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:83"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:83$2439_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
|
||||
wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:91$2440_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
|
||||
wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:118$2445_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
|
||||
wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:132$2448_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
|
||||
wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
|
||||
wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2460_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
|
||||
wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2462_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
|
||||
wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
|
||||
wire width 16 $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
|
||||
wire width 8 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2419_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
|
||||
wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2420_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
|
||||
wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
|
||||
wire width 32 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:56$2423_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
|
||||
wire width 32 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:63$2432_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:65"
|
||||
wire width 16 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:50"
|
||||
wire \addr_lsb
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:24"
|
||||
wire width 32 \ahbls_haddr
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:28"
|
||||
wire width 3 \ahbls_hburst
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:30"
|
||||
wire \ahbls_hmastlock
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:29"
|
||||
wire width 4 \ahbls_hprot
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:32"
|
||||
wire width 32 \ahbls_hrdata
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:22"
|
||||
wire \ahbls_hready
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:21"
|
||||
wire \ahbls_hready_resp
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:23"
|
||||
wire \ahbls_hresp
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:27"
|
||||
wire width 3 \ahbls_hsize
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:26"
|
||||
wire width 2 \ahbls_htrans
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:31"
|
||||
wire width 32 \ahbls_hwdata
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:25"
|
||||
wire \ahbls_hwrite
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
|
||||
wire \aphase_full_width
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
|
||||
wire width 2 \bytemask
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
|
||||
wire width 2 \bytemask_noshift
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:17"
|
||||
wire \clk
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:46"
|
||||
wire \hready_r
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:47"
|
||||
wire \long_dphase
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:64"
|
||||
wire width 16 \rdata_buf
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:49"
|
||||
wire \read_dph
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:18"
|
||||
wire \rst_n
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:34"
|
||||
wire width 11 \sram_addr
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:39"
|
||||
wire width 2 \sram_byte_n
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:36"
|
||||
wire \sram_ce_n
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:35"
|
||||
wire width 16 \sram_dq
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:38"
|
||||
wire \sram_oe_n
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:61"
|
||||
wire width 16 \sram_q
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
|
||||
wire width 16 \sram_rdata
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
|
||||
wire width 16 \sram_wdata
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:37"
|
||||
wire \sram_we_n
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
|
||||
wire \we_next
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:48"
|
||||
wire \write_dph
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
|
||||
process $proc$../hdl/mem/ahb_async_sram_halfwidth.v:71$2436
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
|
||||
switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
|
||||
case 1'1
|
||||
case
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
|
||||
switch \ahbls_hready
|
||||
case 1'1
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
|
||||
switch \ahbls_htrans [1]
|
||||
case 1'1
|
||||
case
|
||||
end
|
||||
case
|
||||
attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
|
||||
switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
|
||||
case 1'1
|
||||
case
|
||||
end
|
||||
end
|
||||
end
|
||||
sync posedge \clk
|
||||
sync negedge \rst_n
|
||||
end
|
||||
connect \ahbls_hresp 1'0
|
||||
connect \bytemask_noshift $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
|
||||
connect \bytemask $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
|
||||
connect \aphase_full_width $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
|
||||
connect \we_next $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
|
||||
connect \sram_rdata $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
|
||||
connect \sram_wdata $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
|
||||
connect \ahbls_hrdata { \sram_rdata $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y }
|
||||
connect \ahbls_hready_resp \hready_r
|
||||
end
|
||||
EOT
|
||||
|
||||
synth_ice40 -abc2 -abc9
|
||||
40
tests/techmap/abc9.ys
Normal file
40
tests/techmap/abc9.ys
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
read_verilog <<EOT
|
||||
`define N 256
|
||||
module top(input [`N-1:0] a, output o);
|
||||
wire [`N-2:0] w;
|
||||
assign w[0] = a[0] & a[1];
|
||||
genvar i;
|
||||
generate for (i = 1; i < `N-1; i++)
|
||||
assign w[i] = w[i-1] & a[i+1];
|
||||
endgenerate
|
||||
assign o = w[`N-2];
|
||||
endmodule
|
||||
EOT
|
||||
simplemap
|
||||
dump
|
||||
design -save gold
|
||||
|
||||
abc9 -lut 4
|
||||
|
||||
design -load gold
|
||||
abc9 -lut 4 -fast
|
||||
|
||||
design -load gold
|
||||
scratchpad -copy abc9.script.default.area abc9.script
|
||||
abc9 -lut 4
|
||||
|
||||
design -load gold
|
||||
scratchpad -copy abc9.script.default.fast abc9.script
|
||||
abc9 -lut 4
|
||||
|
||||
design -load gold
|
||||
scratchpad -copy abc9.script.flow abc9.script
|
||||
abc9 -lut 4
|
||||
|
||||
design -load gold
|
||||
scratchpad -copy abc9.script.flow2 abc9.script
|
||||
abc9 -lut 4
|
||||
|
||||
design -load gold
|
||||
scratchpad -copy abc9.script.flow3 abc9.script
|
||||
abc9 -lut 4
|
||||
Loading…
Add table
Add a link
Reference in a new issue