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https://github.com/YosysHQ/yosys
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docs: work on example_synth
Split hardware mapping from `fifo.ys` into `fifo_map.ys`. Reduces size of `fifo.out` log and allows separate yosys calls in the makefile. Some tidy up and minor changes in `fifo.ys` for better discussion. Filled out note on `clean` (changed from `opt_clean`) and introduced `;;`. Highlighted `$memrd` and added a paragraph about it. More detail on the flatten and merging of `fifo_reader` block. Brief discussion on the changes from `$memrd` to `$memrd_v2`.
This commit is contained in:
Krystine Sherwin
parent
50d8c1b258
commit
9f1c445fbf
5 changed files with 159 additions and 1774 deletions
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@ -3,17 +3,21 @@ PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean
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DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc
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DOT_NAMES += rdata_coarse rdata_map_ram rdata_map_ffram rdata_map_gates
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DOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells
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DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse
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MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
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MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells
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DOTS := $(addsuffix .dot,$(DOT_NAMES))
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MAPDOTS := $(addsuffix .dot,$(MAPDOT_NAMES))
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dots: $(DOTS) fifo.out
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dots: $(DOTS) $(MAPDOTS) fifo.out
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$(DOTS) fifo.out: fifo.v fifo.ys
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$(YOSYS) fifo.ys -l fifo.out -Q -T
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$(MAPDOTS): fifo.v fifo_map.ys
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$(YOSYS) fifo_map.ys
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.PHONY: clean
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clean:
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rm -f *.dot
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File diff suppressed because it is too large
Load diff
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@ -18,7 +18,7 @@ select -set new_cells t:$mux t:*dff
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show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc
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# ========================================================
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opt_clean
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clean
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show -notitle -format dot -prefix addr_gen_clean
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# ========================================================
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@ -26,12 +26,15 @@ design -reset
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read_verilog fifo.v
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hierarchy -check -top fifo
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proc
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show -color maroon3 c:fifo_reader -notitle -format dot -prefix rdata_proc o:rdata %ci*
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select -set new_cells t:$memrd
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show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci*
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# ========================================================
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flatten;;
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show -notitle -format dot -prefix rdata_flat o:rdata %ci*
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select -set rdata_path o:rdata %ci*
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select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path
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# ========================================================
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@ -53,54 +56,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdat
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# ========================================================
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design -reset
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read_verilog fifo.v
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synth_ice40 -top fifo -run begin:map_ram
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memory -nomap
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select -set new_cells t:$mem_v2
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select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path
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# turn command echoes off to avoid randomly generated abc file names
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echo off
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# ========================================================
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synth_ice40 -top fifo -run map_ram:map_ffram
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffram:map_gates
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_gates:map_ffs
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_gates @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffs:map_luts
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffs @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_luts:map_cells
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_luts @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_cells:
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_cells @rdata_path
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45
docs/source/code_examples/fifo/fifo_map.ys
Normal file
45
docs/source/code_examples/fifo/fifo_map.ys
Normal file
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@ -0,0 +1,45 @@
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read_verilog fifo.v
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synth_ice40 -top fifo -run begin:map_ram
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# this point should be the same as rdata_coarse
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# ========================================================
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synth_ice40 -top fifo -run map_ram:map_ffram
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffram:map_gates
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_gates:map_ffs
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_gates @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffs:map_luts
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffs @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_luts:map_cells
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_luts @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_cells:
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_cells @rdata_path
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