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Speed up "make test" and related cleanups

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-08-17 14:37:07 +02:00
parent 41191f1ea4
commit 9e940f1276
6 changed files with 22 additions and 12 deletions
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10
tests/various/shregmap.ys
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@ -45,7 +45,7 @@ shregmap -tech xilinx
stat
# show -width
write_verilog -noexpr -norename
# write_verilog -noexpr -norename
select -assert-count 1 t:$_DFF_P_
select -assert-count 2 t:$__XILINX_SHREG_
@ -59,8 +59,8 @@ prep
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports -seq 5 miter
design -load gold
stat
# design -load gold
# stat
design -load gate
stat
# design -load gate
# stat