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67 lines
1.2 KiB
Plaintext
67 lines
1.2 KiB
Plaintext
read_verilog shregmap.v
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design -save read
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design -copy-to model $__SHREG_DFF_P_
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hierarchy -top shregmap_static_test
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prep
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design -save gold
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techmap
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shregmap -init
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opt
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stat
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# show -width
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 2 t:$__SHREG_DFF_P_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
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prep
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 5 miter
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design -load gold
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stat
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design -load gate
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stat
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##########
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design -load read
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design -copy-to model $__XILINX_SHREG_
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hierarchy -top shregmap_variable_test
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prep
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design -save gold
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simplemap t:$dff t:$dffe
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shregmap -tech xilinx
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stat
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# show -width
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# write_verilog -noexpr -norename
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select -assert-count 1 t:$_DFF_P_
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select -assert-count 2 t:$__XILINX_SHREG_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
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prep
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 5 miter
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# design -load gold
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# stat
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# design -load gate
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# stat
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