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Check flops one by one

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This commit is contained in:
Miodrag Milanovic 2019-10-04 08:42:29 +02:00
parent d19f765a58
commit 9e8175fc75
4 changed files with 50 additions and 71 deletions
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40
tests/ecp5/adffs.v
View file

@ -45,43 +45,3 @@ module ndffnr
else else
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
dffs u_dffs (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnr u_ndffnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule

41
tests/ecp5/adffs.ys
View file

@ -1,9 +1,40 @@
read_verilog adffs.v read_verilog adffs.v
design -save read
proc proc
flatten hierarchy -top adff
equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd adff # Constrain all select calls below inside the top module
select -assert-count 4 t:TRELLIS_FF select -assert-count 1 t:TRELLIS_FF
select -assert-count 3 t:LUT4 select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
proc
hierarchy -top adffn
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
proc
hierarchy -top dffs
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
proc
hierarchy -top ndffnr
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D

22
tests/ecp5/dffs.v
View file

@ -13,25 +13,3 @@ module dffe
if ( en ) if ( en )
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input en,
input a,
output b,b1,
);
dff u_dff (
.clk (clk ),
.d (a ),
.q (b )
);
dffe u_ndffe (
.clk (clk ),
.en (en),
.d (a ),
.q (b1 )
);
endmodule

18
tests/ecp5/dffs.ys
View file

@ -1,9 +1,19 @@
read_verilog dffs.v read_verilog dffs.v
hierarchy -top top design -save read
proc proc
flatten hierarchy -top dff
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd dff # Constrain all select calls below inside the top module
select -assert-count 2 t:TRELLIS_FF select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
proc
hierarchy -top dffe
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D