Add support for SVA until statements via Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>

tests/sva/sva_until.sv

@@ -0,0 +1,19 @@
+module top (
+	input clk,
+	input a, b, c, d
+);
+	default clocking @(posedge clk); endclocking
+
+	assert property (
+		a |=> b until_with (c ##1 d)
+	);
+
+`ifndef FAIL
+	assume property (
+		a |=> b && c
+	);
+	assume property (
+		b && c |=> b && d
+	);
+`endif
+endmodule