mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
20 lines
259 B
Systemverilog
20 lines
259 B
Systemverilog
module top (
|
|
input clk,
|
|
input a, b, c, d
|
|
);
|
|
default clocking @(posedge clk); endclocking
|
|
|
|
assert property (
|
|
a |=> b until_with (c ##1 d)
|
|
);
|
|
|
|
`ifndef FAIL
|
|
assume property (
|
|
a |=> b && c
|
|
);
|
|
assume property (
|
|
b && c |=> b && d
|
|
);
|
|
`endif
|
|
endmodule
|