sta: better handling when no timing paths and unused bits

tests/various/sta.ys

@@ -13,3 +13,31 @@ EOT
 
 logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
 sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module top(input i, output o, p);
+assign o = i;
+endmodule
+EOT
+
+logger -expect log "No timing paths found\." 1
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+endmodule
+EOT
+
+sta
+logger -expect-no-warnings