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Test empty switches

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Krystine Sherwin 2026-01-07 13:21:23 +13:00
parent c0e29ef57c
commit 9a09758f56
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19
tests/proc/bug5572.ys Normal file
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@ -0,0 +1,19 @@
read_rtlil << EOT
attribute \top 1
module \top
wire width 1 \sig
wire width 1 \val
process $2
switch \sig [0]
case 1'0
case 1'1
case
assign \val [0] 1'1
end
end
end
EOT
proc_rmdead
proc_clean
select -assert-none p:*