From 9a09758f5683bacad0776d5cf2353c88f986751c Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Wed, 7 Jan 2026 13:21:23 +1300
Subject: [PATCH] Test empty switches

---
 tests/proc/bug5572.ys    | 19 +++++++++++++++++++
 tests/verilog/.gitignore |  1 +
 tests/verilog/bug5572.ys | 15 +++++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 tests/proc/bug5572.ys
 create mode 100644 tests/verilog/bug5572.ys

diff --git a/tests/proc/bug5572.ys b/tests/proc/bug5572.ys
new file mode 100644
index 000000000..1d8f4e514
--- /dev/null
+++ b/tests/proc/bug5572.ys
@@ -0,0 +1,19 @@
+read_rtlil << EOT
+attribute \top 1
+module \top
+  wire width 1 \sig
+  wire width 1 \val
+
+  process $2
+    switch \sig [0]
+      case 1'0
+      case 1'1
+      case
+        assign \val [0] 1'1
+    end
+  end
+end
+EOT
+proc_rmdead
+proc_clean
+select -assert-none p:*
diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
index b16ed0890..6a226989c 100644
--- a/tests/verilog/.gitignore
+++ b/tests/verilog/.gitignore
@@ -1,3 +1,4 @@
+/bug5572.v
 /const_arst.v
 /const_sr.v
 /doubleslash.v
diff --git a/tests/verilog/bug5572.ys b/tests/verilog/bug5572.ys
new file mode 100644
index 000000000..3044e3572
--- /dev/null
+++ b/tests/verilog/bug5572.ys
@@ -0,0 +1,15 @@
+read_rtlil << EOT
+module \top
+  wire \sig
+  wire \val
+  process $2
+    attribute \full_case 1
+    switch \sig
+    end
+  end
+end
+EOT
+
+write_verilog bug5572.v
+design -reset
+read_verilog bug5572.v