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https://github.com/YosysHQ/yosys
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Add proc_rom pass.
This commit is contained in:
Marcelina Kościelnicka
parent
c862b1dbfb
commit
990c9b8e11
5 changed files with 283 additions and 1 deletions
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@ -46,7 +46,7 @@ struct MemRd : RTLIL::AttrObject {
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std::vector<bool> collision_x_mask;
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SigSpec clk, en, arst, srst, addr, data;
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MemRd() : removed(false), cell(nullptr) {}
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MemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {}
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// Returns the address of given subword index accessed by this port.
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SigSpec sub_addr(int sub) {
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@ -5,6 +5,7 @@ OBJS += passes/proc/proc_clean.o
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OBJS += passes/proc/proc_rmdead.o
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OBJS += passes/proc/proc_init.o
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OBJS += passes/proc/proc_arst.o
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OBJS += passes/proc/proc_rom.o
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OBJS += passes/proc/proc_mux.o
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OBJS += passes/proc/proc_dlatch.o
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OBJS += passes/proc/proc_dff.o
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@ -40,6 +40,7 @@ struct ProcPass : public Pass {
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log(" proc_prune\n");
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log(" proc_init\n");
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log(" proc_arst\n");
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log(" proc_rom\n");
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log(" proc_mux\n");
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log(" proc_dlatch\n");
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log(" proc_dff\n");
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@ -55,6 +56,9 @@ struct ProcPass : public Pass {
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log(" -nomux\n");
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log(" Will omit the proc_mux pass.\n");
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log("\n");
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log(" -norom\n");
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log(" Will omit the proc_rom pass.\n");
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log("\n");
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log(" -global_arst [!]<netname>\n");
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log(" This option is passed through to proc_arst.\n");
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log("\n");
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@ -72,6 +76,7 @@ struct ProcPass : public Pass {
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bool ifxmode = false;
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bool nomux = false;
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bool noopt = false;
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bool norom = false;
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log_header(design, "Executing PROC pass (convert processes to netlists).\n");
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log_push();
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@ -95,6 +100,10 @@ struct ProcPass : public Pass {
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noopt = true;
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continue;
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}
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if (args[argidx] == "-norom") {
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norom = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -108,6 +117,8 @@ struct ProcPass : public Pass {
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Pass::call(design, "proc_arst");
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else
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Pass::call(design, "proc_arst -global_arst " + global_arst);
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if (!norom)
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Pass::call(design, "proc_rom");
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if (!nomux)
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Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux");
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Pass::call(design, "proc_dlatch");
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227
passes/proc/proc_rom.cc
Normal file
227
passes/proc/proc_rom.cc
Normal file
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@ -0,0 +1,227 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/mem.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct RomWorker
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{
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RTLIL::Module *module;
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SigMap sigmap;
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int count = 0;
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RomWorker(RTLIL::Module *mod) : module(mod), sigmap(mod) {}
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void do_switch(RTLIL::SwitchRule *sw)
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{
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for (auto cs : sw->cases) {
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do_case(cs);
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}
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if (sw->cases.empty()) {
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log_debug("rejecting switch: no cases\n");
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return;
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}
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if (GetSize(sw->signal) > 30) {
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log_debug("rejecting switch: address too wide\n");
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return;
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}
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// A switch can be converted into ROM when:
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//
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// 1. No case contains a nested switch
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// 2. All cases have the same set of assigned signals
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// 3. All right-hand values in cases are constants
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// 4. All compare values used in cases are fully-defined constants
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// 5. The cases must cover all possible values (possibly by using default case)
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SigSpec lhs;
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dict<SigBit, int> lhs_lookup;
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for (auto &it: sw->cases[0]->actions) {
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for (auto bit: it.first) {
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if (!lhs_lookup.count(bit)) {
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lhs_lookup[bit] = GetSize(lhs);
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lhs.append(bit);
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}
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}
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}
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dict<int, Const> vals;
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Const default_val;
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bool got_default = false;
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for (auto cs : sw->cases) {
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if (!cs->switches.empty()) {
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log_debug("rejecting switch: has nested switches\n");
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return;
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}
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Const val = Const(State::Sm, GetSize(lhs));
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for (auto &it: cs->actions) {
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if (!it.second.is_fully_const()) {
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log_debug("rejecting switch: rhs not const\n");
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return;
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}
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for (int i = 0; i < GetSize(it.first); i++) {
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auto it2 = lhs_lookup.find(it.first[i]);
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if (it2 == lhs_lookup.end()) {
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log_debug("rejecting switch: lhs not uniform\n");
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return;
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}
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val[it2->second] = it.second[i].data;
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}
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}
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for (auto bit: val.bits) {
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if (bit == State::Sm) {
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log_debug("rejecting switch: lhs not uniform\n");
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return;
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}
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}
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for (auto &addr: cs->compare) {
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if (!addr.is_fully_def()) {
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log_debug("rejecting switch: case value has undef bits\n");
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return;
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}
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int a = addr.as_int();
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if (vals.count(a))
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continue;
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vals[a] = val;
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}
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if (cs->compare.empty()) {
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default_val = val;
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got_default = true;
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break;
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}
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}
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int total = 1 << GetSize(sw->signal);
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if (!got_default && GetSize(vals) != total) {
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log_debug("rejecting switch: not all values are covered\n");
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return;
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}
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// TODO: better density heuristic?
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if (GetSize(vals) < 8) {
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log_debug("rejecting switch: not enough values\n");
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return;
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}
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if (total / GetSize(vals) > 4) {
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log_debug("rejecting switch: not enough density\n");
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return;
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}
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// Ok, let's do it.
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SigSpec rdata = module->addWire(NEW_ID, GetSize(lhs));
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Mem mem(module, NEW_ID, GetSize(lhs), 0, total);
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mem.attributes = sw->attributes;
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Const init_data;
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for (int i = 0; i < total; i++) {
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auto it = vals.find(i);
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if (it == vals.end()) {
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log_assert(got_default);
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for (auto bit: default_val.bits)
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init_data.bits.push_back(bit);
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} else {
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for (auto bit: it->second.bits)
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init_data.bits.push_back(bit);
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}
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}
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MemInit init;
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init.addr = 0;
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init.data = init_data;
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init.en = Const(State::S1, GetSize(lhs));
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mem.inits.push_back(std::move(init));
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MemRd rd;
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rd.addr = sw->signal;
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rd.data = rdata;
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rd.init_value = Const(State::Sx, GetSize(lhs));
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rd.arst_value = Const(State::Sx, GetSize(lhs));
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rd.srst_value = Const(State::Sx, GetSize(lhs));
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mem.rd_ports.push_back(std::move(rd));
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mem.emit();
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for (auto cs: sw->cases)
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delete cs;
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sw->cases.clear();
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sw->signal = SigSpec();
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RTLIL::CaseRule *cs = new RTLIL::CaseRule;
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cs->actions.push_back(SigSig(lhs, rdata));
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sw->cases.push_back(cs);
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count += 1;
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}
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void do_case(RTLIL::CaseRule *cs)
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{
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for (auto sw: cs->switches) {
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do_switch(sw);
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}
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}
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void do_process(RTLIL::Process *pr)
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{
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do_case(&pr->root_case);
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}
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};
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struct ProcRomPass : public Pass {
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ProcRomPass() : Pass("proc_rom", "convert switches to ROMs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_rom [selection]\n");
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log("\n");
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log("This pass converts switches into read-only memories when appropriate.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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int total_count = 0;
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log_header(design, "Executing PROC_ROM pass (convert switches to ROMs).\n");
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extra_args(args, 1, design);
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for (auto mod : design->modules()) {
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if (!design->selected(mod))
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continue;
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RomWorker worker(mod);
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for (auto &proc_it : mod->processes) {
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if (!design->selected(mod, proc_it.second))
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continue;
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worker.do_process(proc_it.second);
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}
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total_count += worker.count;
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}
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log("Converted %d switch%s.\n",
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total_count, total_count == 1 ? "" : "es");
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}
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} ProcRomPass;
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PRIVATE_NAMESPACE_END
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43
tests/proc/proc_rom.ys
Normal file
43
tests/proc/proc_rom.ys
Normal file
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@ -0,0 +1,43 @@
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read_verilog << EOT
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module top(input [3:0] a, input en, output [7:0] d);
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always @*
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if (en)
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case(a)
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4'h0: d <= 8'h12;
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4'h1: d <= 8'h34;
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4'h2: d <= 8'h56;
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4'h3: d <= 8'h78;
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4'h4: d <= 8'h9a;
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4'h5: d <= 8'hbc;
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4'h6: d <= 8'hde;
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4'h7: d <= 8'hff;
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4'h8: d <= 8'h61;
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4'h9: d <= 8'h49;
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4'ha: d <= 8'h36;
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4'hb: d <= 8'h81;
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4'hc: d <= 8'h8c;
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4'hd: d <= 8'ha9;
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4'he: d <= 8'h99;
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4'hf: d <= 8'h51;
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endcase
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else
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d <= 0;
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endmodule
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EOT
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hierarchy -auto-top
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design -save orig
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proc
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memory
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opt_dff
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design -stash postopt
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design -load orig
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proc -norom
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design -stash preopt
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equiv_opt -assert -run prepare: dummy
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