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44 lines
654 B
Plaintext
44 lines
654 B
Plaintext
read_verilog << EOT
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module top(input [3:0] a, input en, output [7:0] d);
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always @*
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if (en)
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case(a)
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4'h0: d <= 8'h12;
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4'h1: d <= 8'h34;
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4'h2: d <= 8'h56;
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4'h3: d <= 8'h78;
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4'h4: d <= 8'h9a;
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4'h5: d <= 8'hbc;
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4'h6: d <= 8'hde;
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4'h7: d <= 8'hff;
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4'h8: d <= 8'h61;
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4'h9: d <= 8'h49;
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4'ha: d <= 8'h36;
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4'hb: d <= 8'h81;
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4'hc: d <= 8'h8c;
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4'hd: d <= 8'ha9;
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4'he: d <= 8'h99;
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4'hf: d <= 8'h51;
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endcase
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else
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d <= 0;
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endmodule
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EOT
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hierarchy -auto-top
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design -save orig
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proc
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memory
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opt_dff
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design -stash postopt
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design -load orig
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proc -norom
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design -stash preopt
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equiv_opt -assert -run prepare: dummy
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