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Merge pull request #4768 from YosysHQ/krys/refactor_selections

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Refactor full_selection
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KrystalDelusion 2025-04-05 14:15:27 +13:00 • committed by GitHub
commit 98d4355b82
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38 changed files with 700 additions and 263 deletions
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passes/techmap/clockgate.cc
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@ -333,7 +333,7 @@ struct ClockgatePass : public Pass {
dict<ClkNetInfo, GClkNetInfo> clk_nets;
int gated_flop_count = 0;
for (auto module : design->selected_whole_modules()) {
for (auto module : design->selected_unboxed_whole_modules()) {
for (auto cell : module->cells()) {
if (!RTLIL::builtin_ff_cell_types().count(cell->type))
continue;