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Add memory_libmap tests.

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Marcelina Kościelnicka 2022-05-06 16:30:56 +02:00
parent 2a2dc12eb6
commit 982a11c709
22 changed files with 1500 additions and 0 deletions
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12
tests/memlib/memlib_lut.txt Normal file
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ram distributed \RAM_LUT {
abits 4;
width 4;
init any;
cost 4;
port ar "R" {
}
port arsw "RW" {
clock anyedge;
}
}